xapp525\spi4_to_4spi3
.......\.............\hdl
.......\.............\...\verilog
.......\.............\...\.......\generic_sfifo_512x72.v
.......\.............\...\.......\generic_sfifo_512x72.xco
.......\.............\...\.......\spi3_to_spi4_arbiter.v
.......\.............\...\.......\spi3_to_spi4_burst_storage.v
.......\.............\...\.......\spi3_to_spi4_core.v
.......\.............\...\.......\spi3_to_spi4_read.v
.......\.............\...\.......\spi3_to_spi4_top.v
.......\.............\...\.......\spi3_to_spi4_write.v
.......\.............\...\.......\spi4_to_spi3_burst_storage.v
.......\.............\...\.......\spi4_to_spi3_core.v
.......\.............\...\.......\spi4_to_spi3_flow_control.v
.......\.............\...\.......\spi4_to_spi3_read.v
.......\.............\...\.......\spi4_to_spi3_top.v
.......\.............\...\.......\spi4_to_spi3_write.v
.......\.............\...\.......\spi_clk_startup.v
.......\.............\...\.......\spi_pkg.v
.......\.............\...\.......\virtex2.v
.......\.............\...\vhdl
.......\.............\...\....\generic_sfifo_512x72.vhd
.......\.............\...\....\generic_sfifo_512x72.xco
.......\.............\...\....\spi3_to_spi4_arbiter.vhd
.......\.............\...\....\spi3_to_spi4_burst_storage.vhd
.......\.............\...\....\spi3_to_spi4_core.vhd
.......\.............\...\....\spi3_to_spi4_read.vhd
.......\.............\...\....\spi3_to_spi4_top.vhd
.......\.............\...\....\spi3_to_spi4_write.vhd
.......\.............\...\....\spi4_to_spi3_burst_storage.vhd
.......\.............\...\....\spi4_to_spi3_core.vhd
.......\.............\...\....\spi4_to_spi3_flow_control.vhd
.......\.............\...\....\spi4_to_spi3_read.vhd
.......\.............\...\....\spi4_to_spi3_top.vhd
.......\.............\...\....\spi4_to_spi3_write.vhd
.......\.............\...\....\spi_clk_startup.vhd
.......\.............\...\....\spi_pkg.vhd
.......\.............\implement
.......\.............\.........\build_bridge_top
.......\.............\.........\build_bridge_top.bat
.......\.............\.........\constraints
.......\.............\.........\...........\bridge_top.ucf
.......\.............\.........\example_reports
.......\.............\.........\...............\bridge_top.bld
.......\.............\.........\...............\bridge_top.mrp
.......\.............\.........\...............\bridge_top_par.par
.......\.............\.........\fpga
.......\.............\.........\netlists
.......\.............\.........\........\bridge_top.edf
.......\.............\.........\........\generic_sfifo_512x72.edn
.......\.............\.........\........\spi3_to_spi4_top.edf
.......\.............\.........\........\spi4_to_spi3_top.edf
.......\.............\.........\synthesis
.......\.............\.........\.........\verilog
.......\.............\.........\.........\.......\bridge_top.prj
.......\.............\.........\.........\.......\bridge_top.sdc
.......\.............\.........\.........\.......\run_synthesis
.......\.............\.........\.........\.......\run_synthesis.bat
.......\.............\.........\.........\.......\spi3_to_spi4_top.prj
.......\.............\.........\.........\.......\spi3_to_spi4_top.sdc
.......\.............\.........\.........\.......\spi4_to_spi3_top.prj
.......\.............\.........\.........\.......\spi4_to_spi3_top.sdc
.......\.............\.........\.........\vhdl
.......\.............\.........\.........\....\bridge_top.prj
.......\.............\.........\.........\....\bridge_top.sdc
.......\.............\.........\.........\....\run_synthesis
.......\.............\.........\.........\....\run_synthesis.bat
.......\.............\.........\.........\....\spi3_to_spi4_top.prj
.......\.............\.........\.........\....\spi3_to_spi4_top.sdc
.......\.............\.........\.........\....\spi4_to_spi3_top.prj
.......\.............\.........\.........\....\spi4_to_spi3_top.sdc
.......\.............\.........\verilog
.......\.............\.........\.......\bridge_top.v
.......\.............\.........\vhdl
.......\.............\.........\....\bri