Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: clock Download
 Description: The code using verilog language to achieve a 24-hour clock time, hours, minutes, seconds, the clock input 1HZ
 Downloaders recently: [More information of uploader 122248455]
 To Search:
  • [50M] - verilog language sub-frequency module, u
File list (Check if you may need any files): 
clock\clock.v
clock

CodeBus www.codebus.net