ASY_FIFO written with verilog,and it is very usefu - CodeBus

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VHDL-FPGA-Verilog

Title: ASY_FIFO

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
1kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
jjia1223

Description: ASY_FIFO written with verilog,and it is very useful in a GALS system

Downloaders recently: [More information of uploader jjia1223]

To Search:

[apb_bridge] - arm ambm 2.0 primecell algorithm ahb con
[fifo] - Asynchronous fifo on the classic, includ
[Asynchronous_Resets_FILO] - The accuracy of the foreign programming

File list (Check if you may need any files):

ASY_FIFO\ASY_FIFO.v
........\DPRAM.v
ASY_FIFO

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