Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: clockVHDL Download
 Description: Using top-down design methodology, from the second counter module, sub-counting module, when the counting module, time setting module and decoding module of five parts.
 Downloaders recently: [More information of uploader fishmind]
 To Search:
File list (Check if you may need any files):
电子钟VHDL设计.doc
    

CodeBus www.codebus.net