Description: vhdl mixed approach with the schematic design vhdl language to describe the bottom of the module, and then designed the schematic design of the top-level schematic file
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File list (Check if you may need any files):
try2\CNT4B.bsf
....\CNT4B.vhd
....\db\prev_cmp_TRY2.asm.qmsg
....\..\prev_cmp_TRY2.fit.qmsg
....\..\prev_cmp_TRY2.map.qmsg
....\..\prev_cmp_TRY2.qmsg
....\..\prev_cmp_TRY2.sim.qmsg
....\..\prev_cmp_TRY2.tan.qmsg
....\..\TRY2.asm.qmsg
....\..\TRY2.asm_labs.ddb
....\..\TRY2.cbx.xml
....\..\TRY2.cmp.bpm
....\..\TRY2.cmp.cdb
....\..\TRY2.cmp.ecobp
....\..\TRY2.cmp.hdb
....\..\TRY2.cmp.logdb
....\..\TRY2.cmp.rdb
....\..\TRY2.cmp.tdb
....\..\TRY2.cmp0.ddb
....\..\TRY2.cmp_bb.cdb
....\..\TRY2.cmp_bb.hdb
....\..\TRY2.cmp_bb.logdb
....\..\TRY2.cmp_bb.rcf
....\..\TRY2.dbp
....\..\TRY2.db_info
....\..\TRY2.eco.cdb
....\..\TRY2.eds_overflow
....\..\TRY2.fit.qmsg
....\..\TRY2.hier_info
....\..\TRY2.hif
....\..\TRY2.map.bpm
....\..\TRY2.map.cdb
....\..\TRY2.map.ecobp
....\..\TRY2.map.hdb
....\..\TRY2.map.logdb
....\..\TRY2.map.qmsg
....\..\TRY2.map_bb.cdb
....\..\TRY2.map_bb.hdb
....\..\TRY2.map_bb.logdb
....\..\TRY2.pre_map.cdb
....\..\TRY2.pre_map.hdb
....\..\TRY2.psp
....\..\TRY2.pss
....\..\TRY2.rtlv.hdb
....\..\TRY2.rtlv_sg.cdb
....\..\TRY2.rtlv_sg_swap.cdb
....\..\TRY2.sgdiff.cdb
....\..\TRY2.sgdiff.hdb
....\..\TRY2.signalprobe.cdb
....\..\TRY2.sim.cvwf
....\..\TRY2.sim.hdb
....\..\TRY2.sim.qmsg
....\..\TRY2.sim.rdb
....\..\TRY2.sld_design_entry.sci
....\..\TRY2.sld_design_entry_dsc.sci
....\..\TRY2.syn_hier_info
....\..\TRY2.tan.qmsg
....\..\TRY2.tis_db_list.ddb
....\..\wed.wsf
....\DECL7S.bsf
....\DECL7S.vhd
....\DECL7S.vhd.bak
....\TRY2.asm.rpt
....\TRY2.bdf
....\TRY2.done
....\TRY2.fit.rpt
....\TRY2.fit.smsg
....\TRY2.fit.summary
....\TRY2.flow.rpt
....\TRY2.map.rpt
....\TRY2.map.summary
....\TRY2.pin
....\TRY2.pof
....\TRY2.qpf
....\TRY2.qsf
....\TRY2.qws
....\TRY2.sim.rpt
....\TRY2.sof
....\TRY2.tan.rpt
....\TRY2.tan.summary
....\TRY2.vwf
....\db
try2
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