Description: Use verilog and VHDL will be prepared by a 32-bit serial data into parallel data, as the FPGA, and DSP interface (DSP Model: 6205)
To Search:
File list (Check if you may need any files):
serial ports2\ my_first_fpga\db\my_first_fpga_top.eco.cdb
.............\..............\..\my_first_fpga_top.sld_design_entry.sci
.............\..............\my_first_fpga.qpf
.............\..............\my_first_fpga.qws
.............\db\add_sub_gub.tdf
.............\..\altsyncram_9pf1.tdf
.............\..\alt_synch_pipe_oc8.tdf
.............\..\alt_synch_pipe_pc8.tdf
.............\..\a_fefifo_ctc.tdf
.............\..\a_fefifo_htc.tdf
.............\..\a_gray2bin_q4b.tdf
.............\..\a_graycounter_u06.tdf
.............\..\cntr_cta.tdf
.............\..\dcfifo_mmc1.tdf
.............\..\dffpipe_gd9.tdf
.............\..\dffpipe_id9.tdf
.............\..\dffpipe_jd9.tdf
.............\..\dpram_jvr.tdf
.............\..\serialports.asm.qmsg
.............\..\serialports.cbx.xml
.............\..\serialports.cmp.bpm
.............\..\serialports.cmp.cdb
.............\..\serialports.cmp.ecobp
.............\..\serialports.cmp.hdb
.............\..\serialports.cmp.logdb
.............\..\serialports.cmp.rdb
.............\..\serialports.cmp.tdb
.............\..\serialports.cmp0.ddb
.............\..\serialports.cmp_bb.cdb
.............\..\serialports.cmp_bb.hdb
.............\..\serialports.cmp_bb.logdb
.............\..\serialports.cmp_bb.rcf
.............\..\serialports.dbp
.............\..\serialports.db_info
.............\..\serialports.eco.cdb
.............\..\serialports.fit.qmsg
.............\..\serialports.hier_info
.............\..\serialports.hif
.............\..\serialports.map.bpm
.............\..\serialports.map.cdb
.............\..\serialports.map.ecobp
.............\..\serialports.map.hdb
.............\..\serialports.map.logdb
.............\..\serialports.map.qmsg
.............\..\serialports.map_bb.cdb
.............\..\serialports.map_bb.hdb
.............\..\serialports.map_bb.logdb
.............\..\serialports.pre_map.cdb
.............\..\serialports.pre_map.hdb
.............\..\serialports.psp
.............\..\serialports.pss
.............\..\serialports.rtlv.hdb
.............\..\serialports.rtlv_sg.cdb
.............\..\serialports.rtlv_sg_swap.cdb
.............\..\serialports.sgdiff.cdb
.............\..\serialports.sgdiff.hdb
.............\..\serialports.signalprobe.cdb
.............\..\serialports.sim.cvwf
.............\..\serialports.sld_design_entry.sci
.............\..\serialports.sld_design_entry_dsc.sci
.............\..\serialports.syn_hier_info
.............\..\serialports.tan.qmsg
.............\..\serialports.tis_db_list.ddb
.............\..\wed.wsf
.............\fifo.bsf
.............\fifo.v
.............\fifo_bb.v
.............\fifo_wave0.jpg
.............\fifo_wave1.jpg
.............\fifo_waveforms.html
.............\fregen.bsf
.............\fregen.v
.............\rec.bsf
.............\rec.v
.............\rec1.v
.............\serialports.asm.rpt
.............\serialports.bdf
.............\serialports.bsf
.............\serialports.cdf
.............\serialports.done
.............\serialports.dpf
.............\serialports.fit.rpt
.............\serialports.fit.smsg
.............\serialports.fit.summary
.............\serialports.flow.rpt
.............\serialports.map.rpt
.............\serialports.map.smsg
.............\serialports.map.summary
.............\serialports.merge.rpt
.............\serialports.pin
.............\serialports.pof
.............\serialports.qpf
.............\serialports.qsf
.............\serialports.qws
.............\serialports.sim.rpt
.............\serialports.sof
.............\serialports.tan.rpt
.............\serialports.tan.summary
.............\serialports.vwf
.............\serialports_assignment_defaults.qdf