Description: Some recent examples of VHDL language exercises, including some simple logic circuit design, running most of the successful, there may be some small problems, hope that colleagues pointing correction.
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File list (Check if you may need any files):
div\div.qpf
...\div.qsf
...\.b\div.db_info
...\..\div.map.qmsg
...\..\prev_cmp_div.map.qmsg
...\..\div.cmp.rdb
...\..\div.sld_design_entry.sci
...\..\prev_cmp_div.qmsg
...\..\div.pre_map.cdb
...\..\div.rtlv.hdb
...\..\div.eco.cdb
...\..\div.cbx.xml
...\..\div.map.logdb
...\..\div.sgdiff.cdb
...\..\div.fit.qmsg
...\..\div.sld_design_entry_dsc.sci
...\..\div.cmp.logdb
...\..\div.cmp.cdb
...\..\div.rtlv_sg.cdb
...\..\div.map.cdb
...\..\div.rpp.qmsg
...\..\prev_cmp_div.fit.qmsg
...\..\div.asm.qmsg
...\..\div.tan.qmsg
...\..\div.pre_map.hdb
...\..\prev_cmp_div.asm.qmsg
...\..\prev_cmp_div.tan.qmsg
...\..\div.sgate.rvd
...\..\div.rtlv_sg_swap.cdb
...\..\div.hif
...\..\div.hier_info
...\..\div.sgdiff.hdb
...\..\div.map.hdb
...\..\div.sgate_sm.rvd
...\..\div.ace_cmp.cdb
...\..\div.cmp.hdb
...\..\div.atom.rvd
...\..\div.cmp.tdb
...\..\prev_cmp_div.sim.qmsg
...\..\div.sim.qmsg
...\..\div.sim.cvwf
...\..\State_machine.db_info
...\..\div.sim.rdb
...\..\div.syn_hier_info
...\..\div.ace_cmp.hdb
...\..\div.sim.hdb
...\..\div.tis_db_list.ddb
...\..\div.cmp0.ddb
...\..\prev_cmp_State_machine.qmsg
...\..\State_machine.map.qmsg
...\..\State_machine.eco.cdb
...\..\State_machine.cbx.xml
...\..\State_machine.hif
...\..\State_machine.sld_design_entry_dsc.sci
...\..\State_machine.pre_map.hdb
...\..\div.cmp.kpt
...\..\prev_cmp_State_machine.map.qmsg
...\..\State_machine.sld_design_entry.sci
...\..\State_machine.map.hdb
...\..\State_machine.cmp.rdb
...\..\State_machine.tis_db_list.ddb
...\..\div.eds_overflow
...\..\wed.wsf
...\div.map.summary
...\div.vhd.bak
...\div.vhd
...\incremental_db\compiled_partitions\div.root_partition.map.kpt
...\..............\README
...\div.pin
...\div.fit.smsg
...\div.fit.summary
...\div.tan.summary
...\div.done
...\div.vwf
...\Moore State_machine\moore.vhd.bak
...\...................\moore.vhd
...\sopc_builder_log.txt
...\State_machine.sopc
...\.sopc_builder\install2.ptf
...\.............\install.ptf
...\.............\preferences.xml
...\State_machine.sopcinfo
...\State_machine.qip
...\sopc_add_qip_file.tcl
...\State_machine.ptf
...\State_machine.ptf.pre_generation_ptf
...\State_machine.ptf.8.0
...\div.map.rpt
...\div.fit.rpt
...\div.asm.rpt
...\div.tan.rpt
...\div.flow.rpt
...\div.sim.rpt
...\undo_redo.txt
...\div.qws
...\State_machine.qpf
...\State_machine.qsf
...\State_machine.map.summary
...\State_machine.vhd.bak
...\State_machine.vhd
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