Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: cf_fft_latest.tar Download
 Description: All designs are pipelined with a synchronous enable and reset. 18 bit precision, real and imaginary. Total is 36 bits.
 Downloaders recently: [More information of uploader superzhaoheng]
 To Search:
File list (Check if you may need any files):
53990785cf_fft_latest.tar
    

CodeBus www.codebus.net