Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: light Download
 Description: FPGA clock frequency is 40MHz, cycle through the diodes, each diode light for two seconds
 Downloaders recently: [More information of uploader zhu-h06]
 To Search:
File list (Check if you may need any files):
light\.lso
.....\diode.lso
.....\diode.ngc
.....\diode.ngr
.....\diode.prj
.....\diode.spl
.....\diode.stx
.....\diode.sym
.....\diode.syr
.....\diode.udo
.....\diode.vhd
.....\diode.vhd.bak
.....\diode.xst
.....\diode_summary.html
.....\diode_vhdl.prj
.....\diode_wave.fdo
.....\diode_xst.xrpt
.....\fuse.log
.....\isim\precompiled.exe.sim\ieee\p_0017514958.didat
.....\....\...................\....\p_0774719531.didat
.....\....\...................\....\p_1242562249.didat
.....\....\...................\....\p_1367372525.didat
.....\....\...................\....\p_2592010699.didat
.....\....\...................\....\p_2717149903.didat
.....\....\...................\....\p_3039841270.didat
.....\....\...................\....\p_3499444699.didat
.....\....\...................\....\p_3564397177.didat
.....\....\...................\....\p_3620187407.didat
.....\....\...................\....\p_3972351953.didat
.....\....\...................\....\p_4165608084.didat
.....\....\...................\std\textio.didat
.....\....\temp\test.vdb
.....\....\....\time_2s.vdb
.....\....\..st_isim_beh.exe.sim\GDBMI-In.txt
.....\....\.....................\GDBMI-Out.txt
.....\....\.....................\isimcrash.log
.....\....\.....................\ISimEngine-DesignHierarchy.dbg
.....\....\.....................\isimkernel.log
.....\....\.....................\netId.dat
.....\....\.....................\test_isim_beh.exe
.....\....\.....................\.mp_save\_1
.....\....\.....................\work\a_1985558087_2372691052.c
.....\....\.....................\....\a_1985558087_2372691052.didat
.....\....\.....................\....\a_1985558087_2372691052.nt.obj
.....\....\.....................\....\a_3210155839_3212880686.c
.....\....\.....................\....\a_3210155839_3212880686.didat
.....\....\.....................\....\a_3210155839_3212880686.nt.obj
.....\....\.....................\....\test_isim_beh.exe_main.c
.....\....\.....................\....\test_isim_beh.exe_main.nt.obj
.....\....\work\test.vdb
.....\....\....\time_2s.vdb
.....\isim.cmd
.....\isim.log
.....\light.gise
.....\light.ise
.....\light.ntrc_log
.....\light.xise
.....\....._xdb\cst.xbcd
.....\.........\tmp\ise\version
.....\.........\...\...\__OBJSTORE__\HierarchicalDesign\HDProject\HDProject
.....\.........\...\...\............\..................\.........\HDProject_StrTbl
.....\.........\...\...\............\..................\__stored_object_table__
.....\.........\...\...\............\PnAutoRun\Scripts\RunOnce_tcl
.....\.........\...\...\............\.........\.......\RunOnce_tcl_StrTbl
.....\.........\...\...\............\.rojectNavigator\dpm_project_main\dpm_project_main
.....\.........\...\...\............\................\................\dpm_project_main_StrTbl
.....\.........\...\...\............\................Gui\CViewSelector
.....\.........\...\...\............\...................\CViewSelector_StrTbl
.....\.........\...\...\............\...................\File-SynthesisOnly
.....\.........\...\...\............\...................\File-SynthesisOnly_StrTbl
.....\.........\...\...\............\...................\Library-SynthesisOnly
.....\.........\...\...\............\...................\Library-SynthesisOnly_StrTbl
.....\.........\...\...\............\...................\Process-BehavioralSim-
.....\.........\...\...\............\...................\Process-BehavioralSim-DESUT_SCHEMATIC
.....\.........\...\...\............\...................\Process-BehavioralSim-DESUT_SCHEMATIC_StrTbl
.....\.........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG
.....\.........\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl
.....\.........\...\...\............\...................\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE
.....\.........\...\...\............\...................\Process-BehavioralSim-DESUT_VHDL_ARCHITECTURE_StrTbl
.....\.........\...\...\............\...................\Process-BehavioralSim-_StrTbl
.....\.........\...\...\............\...................\Process-SynthesisOnly-
....

CodeBus www.codebus.net