Description: library ieee
use ieee.std_logic_1164.all
use ieee.std_logic_unsigned.all
entity exp7_10 is
port( clk: in std_logic
d: in std_logic
clr: in std_logic
en,s:in std_logic
q: out std_logic
)
end exp7_10
architecture bhv of exp7_10 is
signal q1: std_logic
begin
process(clk)
begin
if(clk event and clk= 1 ) then
if(en= 1 ) then
if(clr= 1 ) then q1<= 0
elsif(s= 1 ) then q1<= 1
else q1<=d
end if
end if
end if
end process
q<=q1
end bhv
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