Description: In the half adder using verilog on the basis of a full adder, simple and clever, very helpful for the FPGA Starter
To Search:
File list (Check if you may need any files):
full_adder\add_full4.v
..........\full_adder.qpf
..........\full_adder.qsf
..........\db\full_adder.db_info
..........\..\full_adder.hif
..........\..\full_adder.cbx.xml
..........\..\full_adder.map_bb.hdbx
..........\..\full_adder.map.qmsg
..........\..\full_adder.hier_info
..........\..\full_adder.rtlv_sg.cdb
..........\..\full_adder.rtlv.hdb
..........\..\full_adder.rtlv_sg_swap.cdb
..........\..\full_adder.pre_map.hdb
..........\..\full_adder.pre_map.cdb
..........\..\full_adder.psp
..........\..\full_adder.root_partition.map.info
..........\..\full_adder.map_bb.logdb
..........\..\full_adder.sgdiff.cdb
..........\..\full_adder.sgdiff.hdb
..........\..\full_adder.syn_hier_info
..........\..\full_adder.root_partition.map.atm
..........\..\full_adder.root_partition.map.hdbx
..........\..\full_adder.map_bb.cdb
..........\..\full_adder.map_bb.hdb
..........\..\full_adder.map.ecobp
..........\..\full_adder.map.cdb
..........\..\full_adder.map.hdb
..........\..\full_adder.map.logdb
..........\..\full_adder.map.bpm
..........\..\full_adder.fit.qmsg
..........\..\full_adder.cmp.logdb
..........\..\full_adder.cmp.bpm
..........\..\full_adder.cmp.ecobp
..........\..\full_adder.root_partition.cmp.rcf
..........\..\full_adder.root_partition.cmp.hdbx
..........\..\full_adder.root_partition.cmp.atm
..........\..\full_adder.root_partition.cmp.logdb
..........\..\full_adder.root_partition.cmp.dfp
..........\..\full_adder.tis_db_list.ddb
..........\..\full_adder.asm.qmsg
..........\..\full_adder.asm_labs.ddb
..........\..\full_adder.tan.qmsg
..........\..\full_adder.cmp.tdb
..........\..\full_adder.cmp0.ddb
..........\..\full_adder.cmp.cdb
..........\..\full_adder.signalprobe.cdb
..........\..\full_adder.cmp.hdb
..........\..\full_adder.cmp.rdb
..........\..\prev_cmp_full_adder.map.qmsg
..........\..\prev_cmp_full_adder.fit.qmsg
..........\..\prev_cmp_full_adder.asm.qmsg
..........\..\prev_cmp_full_adder.tan.qmsg
..........\..\full_adder.rpp.qmsg
..........\..\full_adder.sgate.rvd
..........\..\full_adder.sgate_sm.rvd
..........\..\full_adder.eds_overflow
..........\..\wed.wsf
..........\..\full_adder.fnsim.qmsg
..........\..\full_adder.fnsim.cdb
..........\..\full_adder.fnsim.hdb
..........\..\full_adder.sld_design_entry_dsc.sci
..........\..\prev_cmp_full_adder.sim.qmsg
..........\..\prev_cmp_full_adder.qmsg
..........\..\full_adder.sim.qmsg
..........\..\full_adder.sim.hdb
..........\..\full_adder.simfam
..........\..\full_adder.sim.cvwf
..........\..\full_adder.sim.rdb
..........\..\full_adder.sld_design_entry.sci
..........\..\full_adder.eco.cdb
..........\..\full_adder.tmw_info
..........\full_adder.map.summary
..........\full_adder_description.txt
..........\full_adder.map.rpt
..........\full_adder.pin
..........\full_adder.fit.smsg
..........\full_adder.fit.summary
..........\full_adder.fit.rpt
..........\full_adder.sof
..........\full_adder.pof
..........\full_adder.asm.rpt
..........\full_adder.tan.summary
..........\full_adder.tan.rpt
..........\full_adder.flow.rpt
..........\full_adder.done
..........\full_adder.vwf
..........\full_adder.sim.rpt
..........\四位全加器.doc
..........\全加器.bmp
..........\full_adder.qws
..........\db
full_adder