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LIP2301CORE_Synthesisable-RAM

  • Category : Embeded-SCM Develop
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  • Update : 2012-11-26
  • Size : 209kb
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  • Author :j***
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Introduction - If you have any usage issues, please Google them yourself
Verilog Synthesisable RAM source code
Packet file list
(Preview for download)
syn_ram\automake.log
.......\or1200_dpram.cmd_log
.......\or1200_dpram.lso
.......\or1200_dpram.ngr
.......\or1200_dpram.prj
.......\or1200_dpram.syr
.......\or1200_dpram.v
.......\or1200_dpram_summary.html
.......\or1200_dpram_vhdl.prj
.......\or1200_tpram.cmd_log
.......\or1200_tpram.lso
.......\or1200_tpram.ngr
.......\or1200_tpram.prj
.......\or1200_tpram.syr
.......\or1200_tpram_summary.html
.......\or1200_tpram_vhdl.prj
.......\Project.dhp
.......\syn_ram.dhp
.......\syn_ram.ise
.......\syn_ram.ise_ISE_Backup
.......\__projnav.log
.......\.........\ednTOngd_tcl.rsp
.......\.........\or1200_dpram.xst
.......\.........\or1200_tpram.xst
.......\.........\parentCreateTimingConstraintsApp_tcl.rsp
.......\.........\runXst_tcl.rsp
.......\.........\sumrpt_tcl.rsp
.......\.........\syn_ram.gfl
.......\.........\syn_ram_flowplus.gfl
.......\xst\work\hdllib.ref
.......\...\....\vlg1F\or1200__tpram.bin
.......\...\....\...0F\or1200__dpram.bin
or1200_dpram.pdf
or1200_dpram.v
or1200_dpram_fast_syn.lib
or1200_dpram_slow_syn.lib
or1200_dpram_typical_syn.lib
or1200_tpram.pdf
or1200_tpram.v
or1200_tpram_fast_syn.lib
or1200_tpram_slow_syn.lib
or1200_tpram_typical_syn.lib
syn_ram\xst\dump.xst\or1200_tpram.prj\ngx\opt
.......\...\........\................\...\notopt
.......\...\........\.......dpram.prj\ngx\opt
.......\...\........\................\...\notopt
.......\...\........\.......tpram.prj\ngx
.......\...\........\.......dpram.prj\ngx
.......\...\work\vlg1F
.......\...\....\vlg0F
.......\...\dump.xst\or1200_tpram.prj
.......\...\........\or1200_dpram.prj
.......\...\work
.......\...\dump.xst
.......\__projnav
.......\_xmsgs
.......\xst
syn_ram
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