Title:
clock-synchronized-registers
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Description: In general, CPU clock will read and write the introduction to the PLD, the author uses the CPU to read and write clock synchronized read and write registers, improve design reliability. This modeling approach is therefore recommended to read and write CPU registers modeling methods PLD
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使用CPU读写时钟同步方式读写PLD寄存器\asyn_bad\asyn_bad.prd
....................................\........\asyn_bad.prj
....................................\........\decode.v
....................................\........\read_reg.v
....................................\........\..v_1\AutoConstraint_top.sdc
....................................\........\.....\decode.edn
....................................\........\.....\decode.fse
....................................\........\.....\decode.prf
....................................\........\.....\decode.srm
....................................\........\.....\decode.srr
....................................\........\.....\decode.srs
....................................\........\.....\decode.tlg
....................................\........\.....\generic.fse
....................................\........\.....\generic.srd
....................................\........\.....\syntmp\decode.msg
....................................\........\.....\......\decode.plg
....................................\........\top.v
....................................\........\write_reg.v
....................................\oe_edge\decode.v
....................................\.......\oe_edge.prd
....................................\.......\oe_edge.prj
....................................\.......\read_reg.v
....................................\.......\..v_2\AutoConstraint_top.sdc
....................................\.......\.....\generic.fse
....................................\.......\.....\generic.srd
....................................\.......\.....\syntmp\top.msg
....................................\.......\.....\......\top.plg
....................................\.......\.....\top.edn
....................................\.......\.....\top.fse
....................................\.......\.....\top.prf
....................................\.......\.....\top.srm
....................................\.......\.....\top.srr
....................................\.......\.....\top.srs
....................................\.......\.....\top.tlg
....................................\.......\top.v
....................................\.......\write_reg.v
....................................\syn_wr\decode.v
....................................\......\read_reg.v
....................................\......\..v_1\generic.fse
....................................\......\.....\generic.srd
....................................\......\.....\syntmp\top.msg
....................................\......\.....\......\top.plg
....................................\......\.....\top.edn
....................................\......\.....\top.fse
....................................\......\.....\top.prf
....................................\......\.....\top.srm
....................................\......\.....\top.srr
....................................\......\.....\top.srs
....................................\......\.....\top.tlg
....................................\......\syntmp.msg
....................................\......\syn_wr.prd
....................................\......\syn_wr.prj
....................................\......\top.v
....................................\......\write_reg.v
....................................\说明.doc
....................................\asyn_bad\rev_1\syntmp
....................................\oe_edge\rev_2\syntmp
....................................\syn_wr\rev_1\syntmp
....................................\asyn_bad\rev_1
....................................\oe_edge\rev_2
....................................\syn_wr\rev_1
....................................\asyn_bad
....................................\oe_edge
....................................\syn_wr
使用CPU读写时钟同步方式读写PLD寄存器
