SERDES Verilog-based serial and parallel converter

Title: SERDES

Category:
software engineering
Tags:
[WORD]
File Size:
767kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
407327721

Description: Verilog-based serial and parallel converter design and implementation of two different programs to achieve the string and and and string conversion functions, and use the ISE software simulation and debugging chipscope

Downloaders recently: [More information of uploader 407327721]

To Search: serdes veril serdes serdes verilog code serdes verilog XC6SLX4

[S2P_xapp194] - VHDL, verilog Series and conversion comp
[MIT_MIPS_Core.tar] - a Massachusetts Institute of Technology
[FPGA_bit_clock_data_recovery] - New FPGA-based data bit sync clock extra
[serial] - Serial port data transmission experiment
[Design_of_a_6.25_Gbps_Backplane_SerDes_with_TOP-do] - SerDes top-down design methodology proce
[TX] - The launch of a video PDH client, VHDL s
[ser_par] - 24bitAD data sampling and converted to s
[CMI] - Based on FPGA/CPLD' s CMI codec desig
[huawei-fpga-pcb-dg-rules] - Huawei' s specifications, including t
[cbzh] - String and convert the verilog file with

File list (Check if you may need any files):

SERDES.doc

Main Category

SourceCode

Web Code

Develop Tools

Document

Other resource

Category

About site

CodeBus www.codebus.net