codeb_generator5.6 B码校时（B码的产生）用来产生B码，实现B码校时使设备进行同

Title: codeb_generator5.6

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Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
5kb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
gumingsiyizhc

Description: B码校时（B码的产生）用来产生B码，实现B码校时使设备进行同步。

Downloaders recently: [More information of uploader gumingsiyizhc]

To Search:

[codeb_generator5] - B generated code when using the B codes
[IRIG_Standard] - this is IRIG_Standard.
[FPGA-source-code-in-IRIG_B-Design] - FPGA source code in IRIG_B Design

File list (Check if you may need any files):

codeb_generator5.6\chao_zhang.qpf
..................\chao_zhang.qsf
..................\codeb_generator.v.bak
..................\encode_irig_B.v.bak
..................\encode_irig_B.v
..................\codeb_generator.v
..................\chao_zhang.qws
..................\db\chao_zhang.db_info
..................\..\chao_zhang.sld_design_entry.sci
..................\..\chao_zhang.eco.cdb
..................\db
codeb_generator5.6

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