Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: syn_clk Download
 Description: A cross-clock domain clock synchronization methods, including the source files and test files ~
 Downloaders recently: [More information of uploader hjcya-9]
 To Search:
  • [rec] - ram' s written procedures
  • [project] - Sample code of Those things regarding to
File list (Check if you may need any files): 
syn_clk\clk_syn.v
.......\tb_clk_syn.v
syn_clk

CodeBus www.codebus.net