Description: FPGA-based implementation of the I2C interface design, complete code, and a complete test code, ISE can directly open,
To Search:
- [128 × 16ram] - VHDL program designed RAM memory, dual p
- [at24c02] - FPGA-based 24C02 driver, the use of fini
- [I2C] - The use of a standard IIC write VHDL cod
- [VGA] - Verilog code can be ported to FPGA, usin
- [VHDL_code] - FPGA-based AD, DA, LCD, LED, CAN, I2C, P
File list (Check if you may need any files):
I2C\automake.log
...\coregen.log
...\coregen.prj
...\I2C.dhp
...\i2c_master_bit_ctrl.cmd_log
...\i2c_master_bit_ctrl.lso
...\i2c_master_bit_ctrl.ngc
...\i2c_master_bit_ctrl.ngr
...\i2c_master_bit_ctrl.prj
...\i2c_master_bit_ctrl.stx
...\i2c_master_bit_ctrl.syr
...\i2c_master_bit_ctrl.v
...\i2c_master_bit_ctrl.v.bak
...\i2c_master_bit_ctrl_vhdl.prj
...\i2c_master_byte_ctrl.cmd_log
...\i2c_master_byte_ctrl.lso
...\i2c_master_byte_ctrl.ngc
...\i2c_master_byte_ctrl.ngr
...\i2c_master_byte_ctrl.prj
...\i2c_master_byte_ctrl.stx
...\i2c_master_byte_ctrl.syr
...\i2c_master_byte_ctrl.v
...\i2c_master_byte_ctrl.v.bak
...\i2c_master_byte_ctrl_vhdl.prj
...\i2c_master_defines.v
...\i2c_master_defines.v.bak
...\i2c_master_top.cmd_log
...\i2c_master_top.lso
...\i2c_master_top.ngc
...\i2c_master_top.ngr
...\i2c_master_top.prj
...\i2c_master_top.stx
...\i2c_master_top.syr
...\i2c_master_top.v
...\i2c_master_top.v.bak
...\i2c_master_top_vhdl.prj
...\i2c_slave_model.fdo
...\i2c_slave_model.ndo
...\i2c_slave_model.udo
...\i2c_slave_model.v
...\i2c_slave_model.v.bak
...\prjname.lso
...\timescale.v
...\transcript
...\tst_bench_top.v
...\wb_master_model.v
...\wb_master_model.v.bak
...\__projnav.log
...\work\_info
...\....\i2c_slave_model\verilog.asm
...\....\...............\_primary.dat
...\....\...............\_primary.vhd
...\....\glbl\verilog.asm
...\....\....\_primary.dat
...\....\....\_primary.vhd
...\....\i2c_master_bit_ctrl\_primary.vhd
...\....\...................\verilog.asm
...\....\...................\_primary.dat
...\....\............yte_ctrl\_primary.vhd
...\....\....................\verilog.asm
...\....\....................\_primary.dat
...\....\wb_master_model\_primary.vhd
...\....\...............\verilog.asm
...\....\...............\_primary.dat
...\....\i2c_master_top\_primary.vhd
...\....\..............\verilog.asm
...\....\..............\_primary.dat
...\....\tst_bench_top\_primary.vhd
...\....\.............\verilog.asm
...\....\.............\_primary.dat
...\I2C_xdb\tmp\npl\version
...\.......\...\ise\__OBJSTORE__\PnAutoRun\Scripts\RunOnce_tcl
...\.......\...\...\............\.........\.......\RunOnce_tcl_StrTbl
...\.......\...\...\............\.rojectNavigatorGui\GuiProjectData
...\.......\...\...\............\...................\GuiProjectData_StrTbl
...\.......\...\...\............\xreport\Gc_RvReportViewer-Current-Module
...\.......\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
...\.......\...\...\............\.......\Gc_RvReportViewer-Module-Data-i2c_master_byte_ctrl
...\.......\...\...\............\.......\Gc_RvReportViewer-Module-Data-i2c_master_byte_ctrl_StrTbl
...\.......\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
...\.......\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
...\.......\...\...\............\ISimPlugin\SignalOrdering1\tst_bench_top_isim_beh.exe
...\.......\...\...\............\..........\...............\tst_bench_top_isim_beh.exe_StrTbl
...\.......\...\...\............\ProjectNavigator\dpm_project_main\dpm_project_main
...\.......\...\...\............\................\................\dpm_project_main_StrTbl
...\.......\...\...\............\................\................\NameMap
...\.......\...\...\............\................\................\NameMap_StrTbl
...\.......\...\...\............\................\__stored_objects__
...\.......\...\...\............\................\__stored_objects___StrTbl
...\.......\...\...\............\................\__stored_object_table__
...\.......\...\...\............\HierarchicalDesign\HDProject\HDProject
...\.......\...\...\............\..................\.........\HDProject_StrTbl
...\.......\...\...\..REGISTRY__\Autonym\regkeys
...\.......\...\...\............\HierarchicalDesign\HDProject\regkeys
...\.......\...\...\............\..................\regkeys
...\.......\...\...\............\ProjectNavigator\regkeys
...\.......\...\...\............\................Gui\regkeys
...\.......\...\...\............\SrcCtrl\regkeys
...\.......\...\...\............\XSLTProcess\regkey
Download