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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: div5 Download
 Description: the div5 which duty_cycle is 50, description language is verilog, can reduce your time!
 Downloaders recently: [More information of uploader liouyingping1983]
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File list (Check if you may need any files): 
div5.v
.b\div5.db_info
..\div5.sld_design_entry.sci
..\div5.eco.cdb
div5.qpf
div5.qsf
div5.qws
db

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