- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 210kb
- Update:
- 2012-11-26
- Downloads:
- 0 Times
- Uploaded by:
- lgbk
Description: 8-3 decoder, to achieve the inverse function of the decoder 3-8, simple, has passed the timing verification.
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File list (Check if you may need any files):
eit8_3\db\edit8_3.asm.qmsg
......\..\edit8_3.asm_labs.ddb
......\..\edit8_3.cbx.xml
......\..\edit8_3.cmp.cdb
......\..\edit8_3.cmp.hdb
......\..\edit8_3.cmp.kpt
......\..\edit8_3.cmp.logdb
......\..\edit8_3.cmp.rdb
......\..\edit8_3.cmp.tdb
......\..\edit8_3.cmp0.ddb
......\..\edit8_3.cmp2.ddb
......\..\edit8_3.dbp
......\..\edit8_3.db_info
......\..\edit8_3.eco.cdb
......\..\edit8_3.eds_overflow
......\..\edit8_3.fit.qmsg
......\..\edit8_3.hier_info
......\..\edit8_3.hif
......\..\edit8_3.map.cdb
......\..\edit8_3.map.hdb
......\..\edit8_3.map.logdb
......\..\edit8_3.map.qmsg
......\..\edit8_3.pre_map.cdb
......\..\edit8_3.pre_map.hdb
......\..\edit8_3.psp
......\..\edit8_3.rtlv.hdb
......\..\edit8_3.rtlv_sg.cdb
......\..\edit8_3.rtlv_sg_swap.cdb
......\..\edit8_3.sgdiff.cdb
......\..\edit8_3.sgdiff.hdb
......\..\edit8_3.signalprobe.cdb
......\..\edit8_3.sim.hdb
......\..\edit8_3.sim.qmsg
......\..\edit8_3.sim.rdb
......\..\edit8_3.sim.vwf
......\..\edit8_3.sld_design_entry.sci
......\..\edit8_3.sld_design_entry_dsc.sci
......\..\edit8_3.syn_hier_info
......\..\edit8_3.tan.qmsg
......\..\wed.zsf
......\edit8_3.asm.rpt
......\edit8_3.done
......\edit8_3.fit.rpt
......\edit8_3.fit.smsg
......\edit8_3.fit.summary
......\edit8_3.flow.rpt
......\edit8_3.hexout
......\edit8_3.map.rpt
......\edit8_3.map.summary
......\edit8_3.pin
......\edit8_3.pof
......\edit8_3.qpf
......\edit8_3.qsf
......\edit8_3.qws
......\edit8_3.sim.rpt
......\edit8_3.sof
......\edit8_3.tan.rpt
......\edit8_3.tan.summary
......\edit8_3.vhd
......\edit8_3.vwf
......\db
eit8_3