- Category:
- VHDL-FPGA-Verilog
- Tags:
-
- File Size:
- 184kb
- Update:
- 2012-11-26
- Downloads:
- 0 Times
- Uploaded by:
- lgbk
Description: A full adder, using the drawing method will be made of two half adder symbol calls for the full adder, adder combination of sake, the method is simple and verified.
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File list (Check if you may need any files):
adder\db\f_adder.asm.qmsg
.....\..\f_adder.asm_labs.ddb
.....\..\f_adder.cbx.xml
.....\..\f_adder.cmp.cdb
.....\..\f_adder.cmp.hdb
.....\..\f_adder.cmp.kpt
.....\..\f_adder.cmp.logdb
.....\..\f_adder.cmp.rdb
.....\..\f_adder.cmp.tdb
.....\..\f_adder.cmp0.ddb
.....\..\f_adder.cmp2.ddb
.....\..\f_adder.dbp
.....\..\f_adder.db_info
.....\..\f_adder.eco.cdb
.....\..\f_adder.eds_overflow
.....\..\f_adder.fit.qmsg
.....\..\f_adder.hier_info
.....\..\f_adder.hif
.....\..\f_adder.map.cdb
.....\..\f_adder.map.hdb
.....\..\f_adder.map.logdb
.....\..\f_adder.map.qmsg
.....\..\f_adder.pre_map.cdb
.....\..\f_adder.pre_map.hdb
.....\..\f_adder.psp
.....\..\f_adder.rtlv.hdb
.....\..\f_adder.rtlv_sg.cdb
.....\..\f_adder.rtlv_sg_swap.cdb
.....\..\f_adder.sgdiff.cdb
.....\..\f_adder.sgdiff.hdb
.....\..\f_adder.signalprobe.cdb
.....\..\f_adder.sim.hdb
.....\..\f_adder.sim.qmsg
.....\..\f_adder.sim.rdb
.....\..\f_adder.sim.vwf
.....\..\f_adder.sld_design_entry.sci
.....\..\f_adder.sld_design_entry_dsc.sci
.....\..\f_adder.syn_hier_info
.....\..\f_adder.tan.qmsg
.....\..\h_adder.db_info
.....\..\h_adder.eco.cdb
.....\..\h_adder.sld_design_entry.sci
.....\..\wed.zsf
.....\f_adder.asm.rpt
.....\f_adder.bdf
.....\f_adder.done
.....\f_adder.fit.rpt
.....\f_adder.fit.smsg
.....\f_adder.fit.summary
.....\f_adder.flow.rpt
.....\f_adder.hexout
.....\f_adder.map.rpt
.....\f_adder.map.summary
.....\f_adder.pin
.....\f_adder.pof
.....\f_adder.qpf
.....\f_adder.qsf
.....\f_adder.qws
.....\f_adder.sim.rpt
.....\f_adder.sof
.....\f_adder.tan.rpt
.....\f_adder.tan.summary
.....\f_adder.vwf
.....\h_adder.bdf
.....\h_adder.bsf
.....\h_adder.qpf
.....\h_adder.qsf
.....\h_adder.qws
.....\db
adder