Description: 3. To design a data width of 8bit, depth is 16 asynchronous FIFO (read and write clock is not the same), when read and write clock frequencies were wrclk = 40MHz, rdclk = 20MHz, the simulation of the logic waveform. 25,50 When the time clock is faster than write clock time (wrclk = 20MHz, rdclk = 40MHz), how to ensure that read data is written into the valid data? Simulation of your design. Question 3 of the synchronization compared FIFO, analysis of synchronous and asynchronous FIFO FIFO different characteristics.
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