ddr2_test A written using Verilog DDR2 controller

Title: ddr2_test

Category:
VHDL-FPGA-Verilog
Tags:
[VHDL] [源码]
File Size:
10.37mb
Update:
2012-11-26
Downloads:
0 Times
Uploaded by:
左洪成

Description: A written using Verilog DDR2 controller (our project in Altera' s FPGA) successful simulation, and used to control the DDR2 in project

Downloaders recently: [More information of uploader 左洪成]

To Search: ddr2 altera ddr2_test Verilog ddr2 memory controller

[128Mb_ddr] - 128Mb DDR verilog source code
[ddr_ddr2_sdram] - NIOS II based on the DDR2 controller, eq
[ddr2_speedway_f07_9_2_1_1] - Getting Started Guide ddr2sdram controll
[Micron_DDR] - Particles as well as the DDR2 SDRAM init
[DDR2] - DDR2 simulation illustrate the illustrat
[mcb_read_write] - Xilinx DDR2 original user interface prog
[ddr_ddr2_sdram9.0] - altera provided ddr_ddr2_sdram9.0, DDR2
[Davinc_DM6446] - Davinc DM6446 classic example (used abov
[Mentorkg_2010] - Modelsim 6.6 crack, can be used for Wind

File list (Check if you may need any files):

ddr2_test\ddr_test.qpf
.........\ddr_test.qsf
.........\ddr_test.map.summary
.........\ddr2_pre_compile_ddr_timing_summary.txt
.........\auto_verify_ddr_timing.tcl
.........\ddr_lib_path.tcl
.........\auto_add_ddr_constraints.tcl
.........\ddr2.qip
.........\ddr_pll_stratixii.v
.........\ddr_pll_stratixii.ppf
.........\ddr_pll_stratixii.bsf
.........\ddr_pll_stratixii_bb.v
.........\ddr_pll_stratixii.qip
.........\ddr2.html
.........\ddr_test.done
.........\pll_waveforms.html
.........\pll_wave0.jpg
.........\pll.ppf
.........\pll.v
.........\pll.bsf
.........\pll_bb.v
.........\pll.qip
.........\ddr_test.map.smsg
.........\remove_add_constraints_for_ddr2.tcl
.........\ddr_test.dpf
.........\ddr_test.pin
.........\ddr_test.fit.smsg
.........\ddr_test.fit.summary
.........\ddr_test_time_limited.sof
.........\ddr_test.jdi
.........\ddr_test.tan.summary
.........\ddr2_post_summary.txt
.........\ddr2_extraction_log.txt
.........\ddr2_extraction_failures.txt
.........\extraction_min_allnodes.txt
.........\extraction_max_allnodes.txt
.........\ddr2_extraction_data.txt
.........\ddr2_EP2S90_stratixii-c4_paths.txt
.........\ddr2_estimated_data.dat
.........\ddr2_extraction_log2.txt
.........\ddr2.v
.........\ddr2_bb.v
.........\ddr2.bsf
.........\ddr2_ddr_settings.txt
.........\ddr2_auk_ddr_sdram.v
.........\ddr2_auk_ddr_dll.v
.........\ddr_test_1.v
.........\ddr2_auk_ddr_clk_gen.v
.........\ddr2_auk_ddr_datapath.v
.........\ddr2_auk_ddr_dqs_group.v
.........\verify_timing_for_ddr2.tcl
.........\add_constraints_for_ddr2.tcl
.........\constraints_out.txt
.........\ddr2.ppf
.........\rom_waveforms.html
.........\rom_wave0.jpg
.........\rom.v
.........\rom.bsf
.........\rom_bb.v
.........\rom.qip
.........\counter_waveforms.html
.........\counter_wave0.jpg
.........\counter.v
.........\counter.bsf
.........\counter_bb.v
.........\counter.qip
.........\rom_wave1.jpg
.........\ddr_test.mif
.........\ddr2_example_driver.v
.........\ddr_test.fit.rpt
.........\ddr_test.asm.rpt
.........\ddr_test.tan.rpt
.........\stp1.stp
.........\ddd_pll_waveforms.html
.........\ddd_pll_wave0.jpg
.........\ddd_pll.ppf
.........\ddd_pll.v
.........\ddd_pll.bsf
.........\ddd_pll_bb.v
.........\ddd_pll.qip
.........\ddr_test.v.bak
.........\ddr_test.v
.........\ddr_test.map.rpt
.........\ddr_test.flow.rpt
.........\ddr_test.qws
.........\...2_test_2\ddr_test.qpf
.........\...........\ddr_test.qsf
.........\...........\ddr_test.map.summary
.........\...........\ddr2_pre_compile_ddr_timing_summary.txt
.........\...........\auto_verify_ddr_timing.tcl
.........\...........\ddr_lib_path.tcl
.........\...........\auto_add_ddr_constraints.tcl
.........\...........\ddr2.qip
.........\...........\ddr_pll_stratixii.v
.........\...........\ddr_pll_stratixii.ppf
.........\...........\ddr_pll_stratixii.bsf
.........\...........\ddr_pll_stratixii_bb.v
.........\...........\ddr_pll_stratixii.qip
.........\...........\ddr2.html
.........\...........\ddr_test.done

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