Description: This is a Verilog language with a set of procedures, mainly familiar with the application development board, and the verilog language
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EX13\modelsim_test\db\modelsim_test.db_info
....\.............\..\modelsim_test.eco.cdb
....\.............\..\modelsim_test.sld_design_entry.sci
....\.............\modelsim_test.asm.rpt
....\.............\modelsim_test.done
....\.............\modelsim_test.eda.rpt
....\.............\modelsim_test.fit.rpt
....\.............\modelsim_test.fit.smsg
....\.............\modelsim_test.fit.summary
....\.............\modelsim_test.flow.rpt
....\.............\modelsim_test.map.rpt
....\.............\modelsim_test.map.summary
....\.............\modelsim_test.pin
....\.............\modelsim_test.qpf
....\.............\modelsim_test.qsf
....\.............\modelsim_test.qws
....\.............\modelsim_test.tan.rpt
....\.............\modelsim_test.tan.summary
....\.............\modelsim_test.v
....\.............\modelsim_test.v.bak
....\.............\modelsim_test_assignment_defaults.qdf
....\.............\simulation\modelsim\maxii_atoms.v
....\.............\..........\........\modelsim_test.vo
....\.............\..........\........\modelsim_test_modelsim.xrf
....\.............\..........\........\modelsim_test_v.sdo
....\.............\..........\........\vtf_test.v
....\.............\..........\........\vtf_test.v.bak
....\.............\..........\modelsim
....\.............\db
....\.............\simulation
....\modelsim_test
EX13
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