Description: The 7-segment FPGA program written with verilog, very good program, do not miss ah
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File list (Check if you may need any files):
LED_7seg
........\component
........\constraint
........\coreconsole
........\designer
........\........\impl1
........\........\.....\designer.log
........\........\.....\designer_genhdl.log
........\........\.....\Display_7seg.adb
........\........\.....\Display_7seg.dtf
........\........\.....\................\verify.log
........\........\.....\Display_7seg.ide_des
........\........\.....\Display_7seg.stp
........\........\.....\Display_7seg.tcl
........\........\.....\Display_7seg_fp
........\........\.....\...............\Display_7seg.log
........\........\.....\...............\Display_7seg.pro
........\........\.....\...............\projectData
........\........\.....\...............\...........\Display_7seg.stp
........\........\.....\simulation
........\hdl
........\...\Display_7seg.v
........\LED_7seg.prj
........\LED_7seg.prj.convert.7.3.bak
........\phy_synthesis
........\simulation
........\..........\meminit.dat
........\..........\modelsim.ini
........\..........\modelsim.ini.sav
........\smartgen
........\........\smartgen.aws
........\stimulus
........\synthesis
........\.........\Display_7seg.areasrr
........\.........\Display_7seg.edn
........\.........\Display_7seg.fse
........\.........\Display_7seg.map
........\.........\Display_7seg.sap
........\.........\Display_7seg.sdf
........\.........\Display_7seg.srd
........\.........\Display_7seg.srm
........\.........\Display_7seg.srr
........\.........\Display_7seg.srs
........\.........\Display_7seg.tap
........\.........\Display_7seg.tlg
........\.........\Display_7seg.v
........\.........\Display_7seg_sdc.sdc
........\.........\Display_7seg_syn.prj
........\.........\stdout.log
........\.........\syntmp
........\.........\......\Display_7seg.msg
........\.........\......\Display_7seg.plg
........\.........\......\latuch.msg
........\.........\......\latuch.plg
........\.........\......\sap.log
........\.........\traplog.tlg
........\viewdraw
........\........\sch
........\........\sym
........\........\vf
........\........\..\project.lst
........\........\viewdraw.ini
........\........\wir
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