Description: VHDL design of an integrated RISC CPU, coupled with external modules, exhausted and 51 single-chip, of course, the lack of many features, but prototype for all to share
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File list (Check if you may need any files):
cpu design\accumulator.bsf
..........\accumulator.vhd
..........\accumulator.vhd.bak
..........\addr.bsf
..........\addr.vhd
..........\addr.vhd.bak
..........\addr_decode.bsf
..........\addr_decode.vhd
..........\addr_decode.vhd.bak
..........\alu.bsf
..........\alu.vhd
..........\alu.vhd.bak
..........\clkchange.bsf
..........\clkchange.vhd
..........\clkchange.vhd.bak
..........\clk_gen.bsf
..........\clk_gen.vhd
..........\clk_gen.vhd.bak
..........\counter.bsf
..........\counter.vhd
..........\counter.vhd.bak
..........\cpu.asm.rpt
..........\cpu.bdf
..........\cpu.done
..........\cpu.dpf
..........\cpu.fit.rpt
..........\cpu.fit.smsg
..........\cpu.fit.summary
..........\cpu.flow.rpt
..........\cpu.map.rpt
..........\cpu.map.summary
..........\cpu.pin
..........\cpu.pof
..........\cpu.qpf
..........\cpu.qsf
..........\cpu.qws
..........\cpu.sim.rpt
..........\cpu.sof
..........\cpu.tan.rpt
..........\cpu.tan.summary
..........\cpu.vwf
..........\cpumain.bsf
..........\cpumain.vhd
..........\cpumain.vhd.bak
..........\cpu_assignment_defaults.qdf
..........\datactl.bsf
..........\datactl.vhd
..........\datactl.vhd.bak
..........\.b\cpu.asm.qmsg
..........\..\cpu.asm.rdb
..........\..\cpu.cbx.xml
..........\..\cpu.cmp.cdb
..........\..\cpu.cmp.hdb
..........\..\cpu.cmp.kpt
..........\..\cpu.cmp.logdb
..........\..\cpu.cmp.rdb
..........\..\cpu.cmp.tdb
..........\..\cpu.cmp0.ddb
..........\..\cpu.db_info
..........\..\cpu.eco.cdb
..........\..\cpu.eds_overflow
..........\..\cpu.fit.qmsg
..........\..\cpu.hier_info
..........\..\cpu.hif
..........\..\cpu.lpc.html
..........\..\cpu.lpc.rdb
..........\..\cpu.lpc.txt
..........\..\cpu.map.cdb
..........\..\cpu.map.hdb
..........\..\cpu.map.logdb
..........\..\cpu.map.qmsg
..........\..\cpu.pre_map.cdb
..........\..\cpu.pre_map.hdb
..........\..\cpu.ram0_ram_1d0cf.hdl.mif
..........\..\cpu.rtlv.hdb
..........\..\cpu.rtlv_sg.cdb
..........\..\cpu.rtlv_sg_swap.cdb
..........\..\cpu.sgdiff.cdb
..........\..\cpu.sgdiff.hdb
..........\..\cpu.sim.cvwf
..........\..\cpu.sim.hdb
..........\..\cpu.sim.qmsg
..........\..\cpu.sim.rdb
..........\..\cpu.sld_design_entry.sci
..........\..\cpu.sld_design_entry_dsc.sci
..........\..\cpu.smart_action.txt
..........\..\cpu.smp_dump.txt
..........\..\cpu.syn_hier_info
..........\..\cpu.tan.qmsg
..........\..\cpu.tis_db_list.ddb
..........\..\cpu.tmw_info
..........\..\cpu_global_asgn_op.abo
..........\..\logic_util_heursitic.dat
..........\..\prev_cmp_cpu.asm.qmsg
..........\..\prev_cmp_cpu.fit.qmsg
..........\..\prev_cmp_cpu.map.qmsg
..........\..\prev_cmp_cpu.qmsg
..........\..\prev_cmp_cpu.sim.qmsg
..........\..\prev_cmp_cpu.tan.qmsg
..........\..\wed.wsf
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