Description: Quartus II was a development tool of CPLD/FPGA by Altera Company. Quartus II provides a fully integrated circuit structure and has nothing with the development package environment, it has all the features of digital logic design, it is including: available schematic, block diagram, VerilogHDL, AHDL and VHDL complete circuit description which save it as a design entity documents, chip (circuit) connection layout editor, LogicLock design method, the user can create and optimize the system, and then add the original system which is smaller or no effect on the performance of the follow-up module, powerful logic synthesis tool, complete The logic circuit functional simulation and timing simulation tools, Timer/Time Series Analysis and critical path analysis which can use SignalTap II embedded logic analysis tool for logical analysis
To Search:
File list (Check if you may need any files):
RS232_FIR
.........\band.vwf
.........\baud.bsf
.........\baud.vhd
.........\baud.vhd.bak
.........\data_rom.bsf
.........\data_rom.vhd
.........\data_rom.vhd.bak
.........\data_rom.vwf
.........\db
.........\..\rs232_fir.db_info
.........\..\rs232_fir.sld_design_entry.sci
.........\dff8.bsf
.........\dff8.vhd
.........\dff8.vhd.bak
.........\dff8.vwf
.........\fir.bsf
.........\fir.vhd
.........\fir.vhd.bak
.........\fir.vwf
.........\fir1.vwf
.........\fir_b.bdf
.........\fir_b.bsf
.........\fir_block.bsf
.........\reciever.bsf
.........\reciever.vhd
.........\reciever.vhd.bak
.........\reciever.vwf
.........\rs232_fir.asm.rpt
.........\rs232_fir.bdf
.........\rs232_fir.cdf
.........\rs232_fir.done
.........\rs232_fir.dpf
.........\rs232_fir.fit.rpt
.........\rs232_fir.fit.smsg
.........\rs232_fir.fit.summary
.........\rs232_fir.flow.rpt
.........\rs232_fir.map.rpt
.........\rs232_fir.map.summary
.........\rs232_fir.pin
.........\rs232_fir.pof
.........\rs232_fir.qpf
.........\rs232_fir.qsf
.........\rs232_fir.qws
.........\rs232_fir.sim.rpt
.........\rs232_fir.sof
.........\rs232_fir.sta.rpt
.........\rs232_fir.sta.summary
.........\rs232_fir.tan.rpt
.........\rs232_fir.tan.summary
.........\rs232_fir_top.vwf
.........\slow.bsf
.........\slow.vhd
.........\strobe_gen.vhd
.........\strobe_gen.vhd.bak
.........\tflop.vhd
.........\top.bsf
.........\top.vhd
.........\top.vhd.bak
.........\transfer.bsf
.........\transfer.vhd
.........\transfer.vhd.bak
.........\transfer.vwf
.........\undo_redo.txt
Download