Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: dso Download
 Description: Fpga-based design of simple digital storage oscilloscope, including sampling, testing the trigger, waveform storage module functions
 Downloaders recently: [More information of uploader pighui007]
 To Search:
File list (Check if you may need any files):
简易存储示波器
..............\db
..............\..\altsyncram_1us1.tdf
..............\..\altsyncram_9us1.tdf
..............\..\altsyncram_d6n1.tdf
..............\..\altsyncram_l6n1.tdf
..............\..\logic_util_heursitic.dat
..............\..\prev_cmp_verilog.asm.qmsg
..............\..\prev_cmp_verilog.drc.qmsg
..............\..\prev_cmp_verilog.fit.qmsg
..............\..\prev_cmp_verilog.map.qmsg
..............\..\prev_cmp_verilog.qmsg
..............\..\prev_cmp_verilog.tan.qmsg
..............\..\verilog.ae.hdb
..............\..\verilog.asm.qmsg
..............\..\verilog.asm.rdb
..............\..\verilog.asm_labs.ddb
..............\..\verilog.cbx.xml
..............\..\verilog.cmp.bpm
..............\..\verilog.cmp.cdb
..............\..\verilog.cmp.ecobp
..............\..\verilog.cmp.hdb
..............\..\verilog.cmp.kpt
..............\..\verilog.cmp.logdb
..............\..\verilog.cmp.rdb
..............\..\verilog.cmp.tdb
..............\..\verilog.cmp0.ddb
..............\..\verilog.cmp2.ddb
..............\..\verilog.cmp_merge.kpt
..............\..\verilog.db_info
..............\..\verilog.eco.cdb
..............\..\verilog.fit.qmsg
..............\..\verilog.hier_info
..............\..\verilog.hif
..............\..\verilog.lpc.html
..............\..\verilog.lpc.rdb
..............\..\verilog.lpc.txt
..............\..\verilog.map.bpm
..............\..\verilog.map.cdb
..............\..\verilog.map.ecobp
..............\..\verilog.map.hdb
..............\..\verilog.map.kpt
..............\..\verilog.map.logdb
..............\..\verilog.map.qmsg
..............\..\verilog.map_bb.cdb
..............\..\verilog.map_bb.hdb
..............\..\verilog.map_bb.logdb
..............\..\verilog.pre_map.cdb
..............\..\verilog.pre_map.hdb
..............\..\verilog.rpp.qmsg
..............\..\verilog.rtlv.hdb
..............\..\verilog.rtlv_sg.cdb
..............\..\verilog.rtlv_sg_swap.cdb
..............\..\verilog.sgate.rvd
..............\..\verilog.sgate_sm.rvd
..............\..\verilog.sgdiff.cdb
..............\..\verilog.sgdiff.hdb
..............\..\verilog.sld_design_entry.sci
..............\..\verilog.sld_design_entry_dsc.sci
..............\..\verilog.smart_action.txt
..............\..\verilog.smp_dump.txt
..............\..\verilog.syn_hier_info
..............\..\verilog.tan.qmsg
..............\..\verilog.tis_db_list.ddb
..............\incremental_db
..............\..............\compiled_partitions
..............\..............\...................\verilog.root_partition.cmp.cdb
..............\..............\...................\verilog.root_partition.cmp.dfp
..............\..............\...................\verilog.root_partition.cmp.hdb
..............\..............\...................\verilog.root_partition.cmp.kpt
..............\..............\...................\verilog.root_partition.cmp.logdb
..............\..............\...................\verilog.root_partition.cmp.rcfdb
..............\..............\...................\verilog.root_partition.cmp.re.rcfdb
..............\..............\...................\verilog.root_partition.map.cdb
..............\..............\...................\verilog.root_partition.map.dpi
..............\..............\...................\verilog.root_partition.map.hdb
..............\..............\...................\verilog.root_partition.map.kpt
..............\..............\README
..............\mak_contr.bsf
..............\mak_contr.qip
..............\mak_contr.v
..............\mak_contr_bb.v
..............\mak_contr_inst.v
..............\mak_contr_inst.v.bak
..............\mak_contr_wave0.jpg
..............\mak_contr_waveforms.html
..............\undo_redo.txt
..............\verilog.asm.rpt
..............\verilog.done
..............\verilog.dpf
..............\verilog.drc.rpt
..............\verilog.fit.rpt
..............\verilog.fit.summary
..............\verilog.flow.rpt
..............\verilog.map.rpt
..............\verilog.map.summary
..............\verilog.pin
..............\verilog.pof
..............\verilog.qpf
..............\verilog.qsf
    

CodeBus www.codebus.net