fre_counter\clk_gen.v
...........\count.v
...........\count_4units.v
...........\fre_counter.cr.mti
...........\fre_counter.mpf
...........\fre_counter.v
...........\led_sel.v
...........\top_sim.v
...........\transform.v
...........\vsim.wlf
...........\wave.do
...........\.ork\clk_gen\verilog.asm
...........\....\.......\_primary.dat
...........\....\.......\_primary.vhd
...........\....\clk_gen
...........\....\.ount\verilog.asm
...........\....\.....\_primary.dat
...........\....\.....\_primary.vhd
...........\....\count
...........\....\....._4units\verilog.asm
...........\....\............\_primary.dat
...........\....\............\_primary.vhd
...........\....\count_4units
...........\....\fre_counter\verilog.asm
...........\....\...........\_primary.dat
...........\....\...........\_primary.vhd
...........\....\fre_counter
...........\....\led_sel\verilog.asm
...........\....\.......\_primary.dat
...........\....\.......\_primary.vhd
...........\....\led_sel
...........\....\top_sim\verilog.asm
...........\....\.......\_primary.dat
...........\....\.......\_primary.vhd
...........\....\top_sim
...........\....\.ransform\verilog.asm
...........\....\.........\_primary.dat
...........\....\.........\_primary.vhd
...........\....\transform
...........\....\_info
...........\work
fre_counter