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Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: AD Download
 Description: Inside is a sampling AD using the VHDL language and its data storage to achieve control, so that we learn learn
 Downloaders recently: [More information of uploader 903976756]
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File list (Check if you may need any files):
AD\shishi\count_radd.bsf
..\......\count_radd.vhd
..\......\count_wadd.bsf
..\......\count_wadd.vhd
..\......\db\altsyncram_evo3.tdf
..\......\..\altsyncram_ijk1.tdf
..\......\..\cntr_cmi.tdf
..\......\..\cntr_isi.tdf
..\......\..\cntr_j3i.tdf
..\......\..\cntr_m3i.tdf
..\......\..\decode_9jf.tdf
..\......\..\decode_ogi.tdf
..\......\..\mux_lgc.tdf
..\......\..\prev_cmp_shishi.asm.qmsg
..\......\..\prev_cmp_shishi.fit.qmsg
..\......\..\prev_cmp_shishi.map.qmsg
..\......\..\prev_cmp_shishi.qmsg
..\......\..\prev_cmp_shishi.tan.qmsg
..\......\..\shishi.db_info
..\......\..\shishi.eco.cdb
..\......\..\shishi.sld_design_entry.sci
..\......\fenpin.bsf
..\......\fenpin.vhd
..\......\fenpin.vhd.bak
..\......\shishi.asm.rpt
..\......\shishi.bdf
..\......\shishi.bsf
..\......\shishi.done
..\......\shishi.dpf
..\......\shishi.fit.rpt
..\......\shishi.fit.smsg
..\......\shishi.fit.summary
..\......\shishi.flow.rpt
..\......\shishi.jdi
..\......\shishi.map.rpt
..\......\shishi.map.summary
..\......\shishi.pin
..\......\shishi.pof
..\......\shishi.qpf
..\......\shishi.qsf
..\......\shishi.qws
..\......\shishi.sof
..\......\shishi.tan.rpt
..\......\shishi.tan.summary
..\......\shishi_assignment_defaults.qdf
..\......\shishi_clk_sel.bsf
..\......\shishi_clk_sel.vhd
..\......\shishi_clk_sel.vhd.bak
..\......\shishi_ram.bsf
..\......\shishi_ram.cmp
..\......\shishi_ram.vhd
..\......\shishi_ram_wave0.jpg
..\......\shishi_ram_wave1.jpg
..\......\shishi_ram_waveforms.html
..\......\stp1.stp
..\......\db
..\shishi
AD
    

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