Description: I do a very frequent use VHDL language program, has been validated, easy to learn
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File list (Check if you may need any files):
div\db\div.analyze_file.qmsg
...\..\div.asm.qmsg
...\..\div.asm_labs.ddb
...\..\div.cbx.xml
...\..\div.cmp.bpm
...\..\div.cmp.cdb
...\..\div.cmp.ecobp
...\..\div.cmp.hdb
...\..\div.cmp.logdb
...\..\div.cmp.rdb
...\..\div.cmp.tdb
...\..\div.cmp0.ddb
...\..\div.cmp2.ddb
...\..\div.db_info
...\..\div.eco.cdb
...\..\div.eds_overflow
...\..\div.fit.qmsg
...\..\div.hier_info
...\..\div.hif
...\..\div.map.bpm
...\..\div.map.cdb
...\..\div.map.ecobp
...\..\div.map.hdb
...\..\div.map.logdb
...\..\div.map.qmsg
...\..\div.map_bb.cdb
...\..\div.map_bb.hdb
...\..\div.map_bb.hdbx
...\..\div.map_bb.logdb
...\..\div.pre_map.cdb
...\..\div.pre_map.hdb
...\..\div.psp
...\..\div.root_partition.cmp.atm
...\..\div.root_partition.cmp.dfp
...\..\div.root_partition.cmp.hdbx
...\..\div.root_partition.cmp.logdb
...\..\div.root_partition.cmp.rcf
...\..\div.root_partition.map.atm
...\..\div.root_partition.map.hdbx
...\..\div.root_partition.map.info
...\..\div.rtlv.hdb
...\..\div.rtlv_sg.cdb
...\..\div.rtlv_sg_swap.cdb
...\..\div.sgdiff.cdb
...\..\div.sgdiff.hdb
...\..\div.signalprobe.cdb
...\..\div.sim.cvwf
...\..\div.sim.hdb
...\..\div.sim.qmsg
...\..\div.sim.rdb
...\..\div.sld_design_entry.sci
...\..\div.sld_design_entry_dsc.sci
...\..\div.syn_hier_info
...\..\div.tan.qmsg
...\..\div.tis_db_list.ddb
...\..\div.tmw_info
...\..\prev_cmp_div.map.qmsg
...\..\prev_cmp_div.qmsg
...\..\prev_cmp_div.sim.qmsg
...\..\wed.wsf
...\div.asm.rpt
...\div.done
...\div.fit.rpt
...\div.fit.smsg
...\div.fit.summary
...\div.flow.rpt
...\div.map.rpt
...\div.map.summary
...\div.pin
...\div.pof
...\div.qpf
...\div.qsf
...\div.qws
...\div.sim.rpt
...\div.sof
...\div.tan.rpt
...\div.tan.summary
...\div.vhd
...\div.vhd.bak
...\div.vwf
...\db
div