Description: This a digital alarm clock design example, did not verify the success of yesterday, I hope some of the achievements in the field of VHDL colleagues for help
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File list (Check if you may need any files):
ALARM_CLOCK\ALARM_CLOCK.bdf
...........\ALARM_CLOCK.done
...........\ALARM_CLOCK.flow.rpt
...........\ALARM_CLOCK.map.rpt
...........\ALARM_CLOCK.map.summary
...........\ALARM_CLOCK.qpf
...........\ALARM_CLOCK.qsf
...........\ALARM_CLOCK.qws
...........\ALARM_COUNTER.bsf
...........\ALARM_COUNTER.vhd
...........\ALARM_REG.bsf
...........\ALARM_REG.vhd
...........\ALARM_REG.vhd.bak
...........\CONTROL.bsf
...........\CONTROL.vhd
...........\db\ALARM_CLOCK.analyze_file.qmsg
...........\..\ALARM_CLOCK.cbx.xml
...........\..\ALARM_CLOCK.cmp.rdb
...........\..\ALARM_CLOCK.db_info
...........\..\ALARM_CLOCK.eco.cdb
...........\..\ALARM_CLOCK.hier_info
...........\..\ALARM_CLOCK.hif
...........\..\ALARM_CLOCK.map.hdb
...........\..\ALARM_CLOCK.map.logdb
...........\..\ALARM_CLOCK.map.qmsg
...........\..\ALARM_CLOCK.pre_map.hdb
...........\..\ALARM_CLOCK.rtlv.hdb
...........\..\ALARM_CLOCK.rtlv_sg.cdb
...........\..\ALARM_CLOCK.rtlv_sg_swap.cdb
...........\..\ALARM_CLOCK.sld_design_entry.sci
...........\..\ALARM_CLOCK.sld_design_entry_dsc.sci
...........\..\ALARM_CLOCK.smp_dump.txt
...........\..\ALARM_CLOCK.tis_db_list.ddb
...........\..\prev_cmp_ALARM_CLOCK.map.qmsg
...........\..\prev_cmp_ALARM_CLOCK.qmsg
...........\DECODER.bsf
...........\DECODER.vhd
...........\DECODER.vhd.bak
...........\DISPLAY_DRIVER.bsf
...........\DISPLAY_DRIVER.vhd
...........\DRIVER.bsf
...........\DRIVER.vhd
...........\DRIVER.vhd.bak
...........\FQ_DIVIDER.bsf
...........\FQ_DIVIDER.vhd
...........\FQ_DIVIDER.vhd.bak
...........\KEYBUFFER.bsf
...........\KEYBUFFER.vhd
...........\KEYBUFFER.vhd.bak
...........\KEY_BUFFER.bsf
...........\P_ALARM.vhd
...........\REG.bsf
...........\REG.vhd
...........\REG.vhd.bak
...........\db
ALARM_CLOCK
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