Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: shizhong Download
 Description: Contains a clock and test modules, month, day and sometimes every second week to determine the timing and automatic running function.
 Downloaders recently: [More information of uploader 475755008]
 To Search:
File list (Check if you may need any files): 
runnian.v
test_clock2.v
clock.v

CodeBus www.codebus.net