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Title: jing-dain--FPGA-cheng-xu Download
 Description: Classical algorithm on the FPGA, including digital programming and display, using Verilog HDL language to write programs, the development board has been tested successfully!
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数码管_FPGA\seg.qsf
...........\segmain.v
...........\7seg_time\7seg.qpf
...........\.........\7seg.qws
...........\.........\clock.v
...........\.........\seg_7.asm.rpt
...........\.........\seg_7.cdf
...........\.........\seg_7.done
...........\.........\seg_7.dpf
...........\.........\seg_7.fit.rpt
...........\.........\seg_7.fit.smsg
...........\.........\seg_7.fit.summary
...........\.........\seg_7.flow.rpt
...........\.........\seg_7.map.rpt
...........\.........\seg_7.map.smsg
...........\.........\seg_7.map.summary
...........\.........\seg_7.pin
...........\.........\seg_7.qpf
...........\.........\seg_7.qsf
...........\.........\seg_7.qws
...........\.........\seg_7.sof
...........\.........\seg_7.tan.rpt
...........\.........\seg_7.tan.summary
...........\.........\seg_7.v
...........\.........\seg_7.pof
...........\.........\db\seg_7.map.hdb
...........\.........\..\seg_7.map.logdb
...........\.........\..\seg_7.map.qmsg
...........\.........\..\seg_7.map_bb.cdb
...........\.........\..\seg_7.map_bb.hdb
...........\.........\..\seg_7.map_bb.logdb
...........\.........\..\seg_7.pre_map.cdb
...........\.........\..\seg_7.pre_map.hdb
...........\.........\..\seg_7.psp
...........\.........\..\seg_7.pss
...........\.........\..\seg_7.rpp.qmsg
...........\.........\..\seg_7.rtlv.hdb
...........\.........\..\seg_7.rtlv_sg.cdb
...........\.........\..\seg_7.rtlv_sg_swap.cdb
...........\.........\..\seg_7.sgate.rvd
...........\.........\..\seg_7.sgate_sm.rvd
...........\.........\..\seg_7.sgdiff.cdb
...........\.........\..\seg_7.sgdiff.hdb
...........\.........\..\seg_7.signalprobe.cdb
...........\.........\..\seg_7.sld_design_entry.sci
...........\.........\..\seg_7.sld_design_entry_dsc.sci
...........\.........\..\seg_7.syn_hier_info
...........\.........\..\seg_7.tan.qmsg
...........\.........\..\seg_7.tis_db_list.ddb
...........\.........\..\7seg.db_info
...........\.........\..\7seg.eco.cdb
...........\.........\..\7seg.sld_design_entry.sci
...........\.........\..\prev_cmp_seg_7.asm.qmsg
...........\.........\..\prev_cmp_seg_7.fit.qmsg
...........\.........\..\prev_cmp_seg_7.map.qmsg
...........\.........\..\prev_cmp_seg_7.qmsg
...........\.........\..\prev_cmp_seg_7.tan.qmsg
...........\.........\..\seg_7.asm.qmsg
...........\.........\..\seg_7.asm_labs.ddb
...........\.........\..\seg_7.atom_map.rvd
...........\.........\..\seg_7.cbx.xml
...........\.........\..\seg_7.cmp.bpm
...........\.........\..\seg_7.cmp.cdb
...........\.........\..\seg_7.cmp.ecobp
...........\.........\..\seg_7.cmp.hdb
...........\.........\..\seg_7.cmp.logdb
...........\.........\..\seg_7.cmp.rdb
...........\.........\..\seg_7.cmp.tdb
...........\.........\..\seg_7.cmp0.ddb
...........\.........\..\seg_7.cmp2.ddb
...........\.........\..\seg_7.cmp_bb.cdb
...........\.........\..\seg_7.cmp_bb.hdb
...........\.........\..\seg_7.cmp_bb.logdb
...........\.........\..\seg_7.cmp_bb.rcf
...........\.........\..\seg_7.dbp
...........\.........\..\seg_7.db_info
...........\.........\..\seg_7.eco.cdb
...........\.........\..\seg_7.fit.qmsg
...........\.........\..\seg_7.hier_info
...........\.........\..\seg_7.hif
...........\.........\..\seg_7.map.bpm
...........\.........\..\seg_7.map.cdb
...........\.........\..\seg_7.map.ecobp
...........\.........\db
...........\7seg_time
数码管_FPGA
    

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