Description: SDRAM read and write for the project is divided into the internal PLL and reset processing module, SDRAM write logic block, logic block read SDRAM, SDRAM modules package to read and write, read and write buffer FIFO module, serial module occurs. Altera-based engineering design of the Quartus II 10.1, the software can be used later.
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test_sdram
..........\datagene.v
..........\datagene.v.bak
..........\db
..........\..\add_sub_918.tdf
..........\..\add_sub_gub.tdf
..........\..\add_sub_se8.tdf
..........\..\altsyncram_1lh1.tdf
..........\..\altsyncram_2lh1.tdf
..........\..\alt_synch_pipe_oc8.tdf
..........\..\alt_synch_pipe_pc8.tdf
..........\..\alt_sync_fifo_0fm.tdf
..........\..\alt_sync_fifo_0oi.tdf
..........\..\alt_sync_fifo_uni.tdf
..........\..\a_fefifo_ctc.tdf
..........\..\a_fefifo_htc.tdf
..........\..\a_gray2bin_q4b.tdf
..........\..\a_graycounter_u06.tdf
..........\..\cntr_cta.tdf
..........\..\cntr_kua.tdf
..........\..\dcfifo_35l1.tdf
..........\..\dcfifo_k2l1.tdf
..........\..\dcfifo_o2l1.tdf
..........\..\dffpipe_gd9.tdf
..........\..\dffpipe_id9.tdf
..........\..\dffpipe_jd9.tdf
..........\..\dpram_4o31.tdf
..........\..\dpram_6o31.tdf
..........\..\logic_util_heursitic.dat
..........\..\prev_cmp_sdr_test.asm.qmsg
..........\..\prev_cmp_sdr_test.eda.qmsg
..........\..\prev_cmp_sdr_test.fit.qmsg
..........\..\prev_cmp_sdr_test.map.qmsg
..........\..\prev_cmp_sdr_test.qmsg
..........\..\prev_cmp_sdr_test.sta.qmsg
..........\..\sdr_test.amm.cdb
..........\..\sdr_test.asm.qmsg
..........\..\sdr_test.asm.rdb
..........\..\sdr_test.atom.rvd
..........\..\sdr_test.atom_map.rvd
..........\..\sdr_test.cbx.xml
..........\..\sdr_test.cmp.bpm
..........\..\sdr_test.cmp.cdb
..........\..\sdr_test.cmp.hdb
..........\..\sdr_test.cmp.kpt
..........\..\sdr_test.cmp.logdb
..........\..\sdr_test.cmp.rdb
..........\..\sdr_test.cmp0.ddb
..........\..\sdr_test.cmp_merge.kpt
..........\..\sdr_test.db_info
..........\..\sdr_test.eda.qmsg
..........\..\sdr_test.fit.qmsg
..........\..\sdr_test.hier_info
..........\..\sdr_test.hif
..........\..\sdr_test.idb.cdb
..........\..\sdr_test.lfp.cdb
..........\..\sdr_test.lpc.html
..........\..\sdr_test.lpc.rdb
..........\..\sdr_test.lpc.txt
..........\..\sdr_test.map.bpm
..........\..\sdr_test.map.cdb
..........\..\sdr_test.map.hdb
..........\..\sdr_test.map.kpt
..........\..\sdr_test.map.logdb
..........\..\sdr_test.map.qmsg
..........\..\sdr_test.map_bb.cdb
..........\..\sdr_test.map_bb.hdb
..........\..\sdr_test.map_bb.logdb
..........\..\sdr_test.pre_map.cdb
..........\..\sdr_test.pre_map.hdb
..........\..\sdr_test.rpp.qmsg
..........\..\sdr_test.rtlv.hdb
..........\..\sdr_test.rtlv_sg.cdb
..........\..\sdr_test.rtlv_sg_swap.cdb
..........\..\sdr_test.sgate.rvd
..........\..\sdr_test.sgate_sm.rvd
..........\..\sdr_test.sgdiff.cdb
..........\..\sdr_test.sgdiff.hdb
..........\..\sdr_test.sld_design_entry.sci
..........\..\sdr_test.sld_design_entry_dsc.sci
..........\..\sdr_test.smart_action.txt
..........\..\sdr_test.smp_dump.txt
..........\..\sdr_test.sta.qmsg
..........\..\sdr_test.sta.rdb
..........\..\sdr_test.sta_cmp.8_slow.tdb
..........\..\sdr_test.syn_hier_info
..........\..\sdr_test.tis_db_list.ddb
..........\..\sdr_test.tmw_info
..........\greybox_tmp
..........\...........\cbx_args.txt
..........\incremental_db
..........\..............\compiled_partitions
..........\..............\...................\sdr_test.db_info
..........\..............\...................\sdr_test.root_partition.cmp.atm
..........\..............\...................\sdr_test.root_partition.cmp.cbp
..........\..............\...................\sdr_test.root_partition.cmp.cdb
..........\..............\...................\sdr_test.root_partition.cmp.dfp
..........\..............\...................\sdr_test.root_partition.cmp.hdb
..........\..............\...................\sdr_test.root_partition.cmp.hdbx
..........\..............\...................\sdr_test.root_partition.cmp.kpt
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