Description: The project is mainly designed to UART receiver module, UART transmit module and receive data through COM port and then sent to the PC uart module.
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File list (Check if you may need any files):
uart_verilog
............\rcvr.bsf
............\rcvr.v
............\segmain.bsf
............\segmain.v
............\segmain.v.bak
............\setup.tcl
............\setup.tcl.bak
............\txmit.bsf
............\txmit.v
............\uart.bsf
............\uart.v
............\uart_send.bsf
............\uart_send.v
............\uart_v.asm.rpt
............\uart_v.bdf
............\uart_v.done
............\uart_v.dpf
............\uart_v.fit.rpt
............\uart_v.fit.smsg
............\uart_v.fit.summary
............\uart_v.flow.rpt
............\uart_v.map.rpt
............\uart_v.map.smsg
............\uart_v.map.summary
............\uart_v.pin
............\uart_v.pof
............\uart_v.qpf
............\uart_v.qsf
............\uart_v.qws
............\uart_v.sof
............\uart_v.tan.rpt
............\uart_v.tan.summary
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