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Title: vhdlClock Download
 Description: Electronic clock program written in VHDL, the simulation is correct, including source code
 Downloaders recently: [More information of uploader liaojiawen]
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File list (Check if you may need any files):
秒表\CLKGEN\CLKGEN.qpf
....\......\CLKGEN.qsf
....\......\db\_desktop.ini
....\......\..\CLKGEN.db_info
....\......\..\CLKGEN.tan.qmsg
....\......\..\CLKGEN.map.qmsg
....\......\..\CLKGEN.sld_design_entry.sci
....\......\..\CLKGEN.cbx.xml
....\......\..\CLKGEN.hif
....\......\..\CLKGEN.hier_info
....\......\..\CLKGEN.rtlv_sg.cdb
....\......\..\CLKGEN.rtlv.hdb
....\......\..\CLKGEN.cmp.tdb
....\......\..\CLKGEN.rtlv_sg_swap.cdb
....\......\..\CLKGEN.pre_map.hdb
....\......\..\CLKGEN.pre_map.cdb
....\......\..\CLKGEN.psp
....\......\..\CLKGEN.pss
....\......\..\CLKGEN.dbp
....\......\..\CLKGEN.map.logdb
....\......\..\CLKGEN.sgdiff.cdb
....\......\..\CLKGEN.sgdiff.hdb
....\......\..\CLKGEN.sld_design_entry_dsc.sci
....\......\..\CLKGEN.syn_hier_info
....\......\..\CLKGEN.map.cdb
....\......\..\CLKGEN.map.hdb
....\......\..\CLKGEN.cmp0.ddb
....\......\..\CLKGEN.fit.qmsg
....\......\..\CLKGEN.cmp.logdb
....\......\..\CLKGEN.cmp.cdb
....\......\..\CLKGEN.signalprobe.cdb
....\......\..\CLKGEN.eco.cdb
....\......\..\CLKGEN.cmp.kpt
....\......\..\CLKGEN.cmp.hdb
....\......\..\CLKGEN.cmp.rdb
....\......\..\CLKGEN.asm.qmsg
....\......\CLKGEN.vhd
....\......\CLKGEN.map.rpt
....\......\CLKGEN.flow.rpt
....\......\CLKGEN.map.summary
....\......\CLKGEN.pin
....\......\CLKGEN.fit.rpt
....\......\CLKGEN.fit.smsg
....\......\CLKGEN.fit.summary
....\......\CLKGEN.sof
....\......\CLKGEN.pof
....\......\CLKGEN.asm.rpt
....\......\CLKGEN.tan.summary
....\......\CLKGEN.tan.rpt
....\......\CLKGEN.done
....\......\CLKGEN.qws
....\......\_desktop.ini
....\.NT6\CNT6.qpf
....\....\CNT6.qsf
....\....\db\wed.zsf
....\....\..\CNT6.db_info
....\....\..\CNT6.asm.qmsg
....\....\..\CNT6.cmp.rdb
....\....\..\CNT6.tan.qmsg
....\....\..\CNT6.cmp.hdb
....\....\..\CNT6.eco.cdb
....\....\..\CNT6.sim.qmsg
....\....\..\CNT6.map.qmsg
....\....\..\CNT6.signalprobe.cdb
....\....\..\CNT6.cmp.tdb
....\....\..\_desktop.ini
....\....\..\CNT6.cbx.xml
....\....\..\CNT6.hif
....\....\..\CNT6.hier_info
....\....\..\CNT6.rtlv_sg.cdb
....\....\..\CNT6.cmp0.ddb
....\....\..\CNT6.rtlv.hdb
....\....\..\CNT6.rtlv_sg_swap.cdb
....\....\..\CNT6.pre_map.hdb
....\....\..\CNT6.pre_map.cdb
....\....\..\CNT6.psp
....\....\..\CNT6.pss
....\....\..\CNT6.dbp
....\....\..\CNT6.map.logdb
....\....\..\CNT6.sgdiff.cdb
....\....\..\CNT6.sgdiff.hdb
....\....\..\CNT6.sld_design_entry_dsc.sci
....\....\..\CNT6.syn_hier_info
....\....\..\CNT6.cmp.cdb
....\....\..\CNT6.map.cdb
....\....\..\CNT6.eds_overflow
....\....\..\CNT6.map.hdb
....\....\..\CNT6.sim.hdb
....\....\..\CNT6.sim.vwf
....\....\..\CNT6.fit.qmsg
....\....\..\CNT6.cmp.logdb
....\....\..\CNT6.sld_design_entry.sci
....\....\..\CNT6.sim.rdb
....\....\..\CNT6.cmp.kpt
....\....\CNT6.vhd
....\....\CNT6.map.rpt
....\....\CNT6.flow.rpt
....\....\CNT6.map.summary
....\....\CNT6.pin
....\....\CNT6.fit.rpt
    

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