Description: A USB2.0 IP core (for details verilog source code and documentation), it is a good reference design
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usb2.0_funct_ip\bench\CVS\Entries
...............\.....\...\Repository
...............\.....\...\Root
...............\.....\verilog\CVS\Entries
...............\.....\.......\...\Repository
...............\.....\.......\...\Root
...............\doc\CVS\Entries
...............\...\...\Repository
...............\...\...\Root
...............\...\README.txt
...............\...\STATUS.txt
...............\...\usb_doc.pdf
...............\rtl\CVS\Entries
...............\...\...\Repository
...............\...\...\Root
...............\...\verilog\CVS\Entries
...............\...\.......\...\Repository
...............\...\.......\...\Root
...............\...\.......\usbf_crc16.v
...............\...\.......\usbf_crc5.v
...............\...\.......\usbf_defines.v
...............\...\.......\usbf_ep_rf.v
...............\...\.......\usbf_ep_rf_dummy.v
...............\...\.......\usbf_idma.v
...............\...\.......\usbf_mem_arb.v
...............\...\.......\usbf_pa.v
...............\...\.......\usbf_pd.v
...............\...\.......\usbf_pe.v
...............\...\.......\usbf_pl.v
...............\...\.......\usbf_rf.v
...............\...\.......\usbf_top.v
...............\...\.......\usbf_utmi_if.v
...............\...\.......\usbf_utmi_ls.v
...............\...\.......\usbf_wb.v
...............\sim\CVS\Entries
...............\...\...\Repository
...............\...\...\Root
...............\...\rtl_sim\bin\CVS\Entries
...............\...\.......\...\...\Repository
...............\...\.......\...\...\Root
...............\...\.......\CVS\Entries
...............\...\.......\...\Repository
...............\...\.......\...\Root
...............\...\.......\run\CVS\Entries
...............\...\.......\...\...\Repository
...............\...\.......\...\...\Root
...............\.yn\bin\comp.dc
...............\...\...\CVS\Entries
...............\...\...\...\Repository
...............\...\...\...\Root
...............\...\...\design_spec.dc
...............\...\...\lib_spec.dc
...............\...\...\read.dc
...............\...\CVS\Entries
...............\...\...\Repository
...............\...\...\Root
...............\...\log\CVS\Entries
...............\...\...\...\Repository
...............\...\...\...\Root
...............\...\out\CVS\Entries
...............\...\...\...\Repository
...............\...\...\...\Root
...............\...\run\CVS\Entries
...............\...\...\...\Repository
...............\...\...\...\Root
...............\.im\rtl_sim\bin\CVS
...............\...\.......\run\CVS
...............\bench\verilog\CVS
...............\rtl\verilog\CVS
...............\sim\rtl_sim\bin
...............\...\.......\CVS
...............\...\.......\run
...............\.yn\bin\CVS
...............\...\log\CVS
...............\...\out\CVS
...............\...\run\CVS
...............\bench\CVS
...............\.....\verilog
...............\doc\CVS
...............\rtl\CVS
...............\...\verilog
...............\sim\CVS
...............\...\rtl_sim
...............\.yn\bin
...............\...\CVS
...............\...\log
...............\...\out
...............\...\run
...............\bench
...............\doc
...............\rtl
...............\sim
...............\syn
usb2.0_funct_ip
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