1_02_FullAdd4\FULLADD.V
.............\FullAdd4.mpf
.............\FULLADD4.V
.............\FULLADD4_test.v
.............\transcript
.............\vsim.wlf
.............\work\@full@add\verilog.asm
.............\....\.........\_primary.dat
.............\....\.........\_primary.vhd
.............\....\.........4\verilog.asm
.............\....\..........\_primary.dat
.............\....\..........\_primary.vhd
.............\....\t\verilog.asm
.............\....\.\_primary.dat
.............\....\.\_primary.vhd
.............\....\_info