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Title: USB_IP-CORE-design Download
 Description: USB2.0 IP core, you need to add additional PHY module, using the Verilog language
 Downloaders recently: [More information of uploader dongjian397]
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File list (Check if you may need any files):
verilog\usbf_crc16.v
.......\usbf_crc5.v
.......\usbf_defines.v
.......\usbf_ep_rf.v
.......\usbf_ep_rf_dummy.v
.......\usbf_idma.v
.......\usbf_mem_arb.v
.......\usbf_pa.v
.......\usbf_pd.v
.......\usbf_pe.v
.......\usbf_pl.v
.......\usbf_rf.v
.......\usbf_top.v
.......\usbf_utmi_if.v
.......\usbf_utmi_ls.v
.......\usbf_wb.v
usb_doc.pdf
verilog
    

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