Description: This application note describes a Virtex ™ -4 XC4VLX25 FF668-10C to implement the DDR SDRAM device controller. The clock control to achieve use of technology to achieve direct data acquisition, and automatic calibration circuit to adjust the data in line delay.
To Search:
File list (Check if you may need any files):
DDR SDRAM
.........\DDR SDRAM
.........\.........\DDR SDRAM
.........\.........\.........\mem_interface_top.txt
.........\.........\.........\mem_interface_top_addr_gen_0.txt
.........\.........\.........\mem_interface_top_backend_fifos_0.txt
.........\.........\.........\mem_interface_top_backend_rom_0.txt
.........\.........\.........\mem_interface_top_cmp_rd_data_0.txt
.........\.........\.........\mem_interface_top_controller_iobs_0.txt
.........\.........\.........\mem_interface_top_data_gen_16.txt
.........\.........\.........\mem_interface_top_data_path_0.txt
.........\.........\.........\mem_interface_top_data_path_iobs_0.txt
.........\.........\.........\mem_interface_top_data_tap_inc.txt
.........\.........\.........\mem_interface_top_data_write_0.txt
.........\.........\.........\mem_interface_top_ddr_controller_0.txt
.........\.........\.........\mem_interface_top_idelay_ctrl.txt
.........\.........\.........\mem_interface_top_infrastructure.txt
.........\.........\.........\mem_interface_top_infrastructure_iobs_0.txt
.........\.........\.........\mem_interface_top_iobs_0.txt
.........\.........\.........\mem_interface_top_main_0.txt
.........\.........\.........\mem_interface_top_parameters_0.txt
.........\.........\.........\mem_interface_top_pattern_compare8.txt
.........\.........\.........\mem_interface_top_RAM_D_0.txt
.........\.........\.........\mem_interface_top_rd_data_0.txt
.........\.........\.........\mem_interface_top_rd_data_fifo_0.txt
.........\.........\.........\mem_interface_top_rd_wr_addr_fifo_0.txt
.........\.........\.........\mem_interface_top_tap_ctrl_0.txt
.........\.........\.........\mem_interface_top_tap_logic_0.txt
.........\.........\.........\mem_interface_top_test_bench_0.txt
.........\.........\.........\mem_interface_top_top_0.txt
.........\.........\.........\mem_interface_top_user_interface_0.txt
.........\.........\.........\mem_interface_top_v4_dm_iob.txt
.........\.........\.........\mem_interface_top_v4_dqs_iob.txt
.........\.........\.........\mem_interface_top_v4_dq_iob.txt
.........\.........\.........\mem_interface_top_wr_data_fifo_16.txt
Download