MSP430和FPGA通信模块四个ROM\430文件夹\inteface\Backup of interface.ewd
...........................\.........\........\Backup of interface.ewp
...........................\.........\........\Debug\Exe\interface.d43
...........................\.........\........\.....\Obj\interface.pbd
...........................\.........\........\.....\...\main.r43
...........................\.........\........\interface.dep
...........................\.........\........\interface.ewd
...........................\.........\........\interface.ewp
...........................\.........\........\interface.eww
...........................\.........\........\main.c
...........................\.........\........\settings\interface.cspy.bat
...........................\.........\........\........\interface.dbgdt
...........................\.........\........\........\interface.dni
...........................\.........\........\........\interface.wsdt
...........................\.........\inteface.rar
...........................\McuCommunication\aa.bsf
...........................\................\ADDR_DFF.bsf
...........................\................\ADDR_DFF.inc
...........................\................\ADDR_DFF.qip
...........................\................\ADDR_DFF.vhd
...........................\................\ads805\ads805.vhd
...........................\................\......\ads805.vhd.bak
...........................\................\control.bsf
...........................\................\control.vhd
...........................\................\control.vhd.bak
...........................\................\counter0.bsf
...........................\................\counter0.inc
...........................\................\counter0.qip
...........................\................\counter0.vhd
...........................\................\counter0_wave0.jpg
...........................\................\counter0_waveforms.html
...........................\................\DAC902.pdf
...........................\................\dds2_core.bsf
...........................\................\DDS_ACC.bsf
...........................\................\DDS_ACC.cmp
...........................\................\DDS_ACC.inc
...........................\................\DDS_ACC.qip
...........................\................\DDS_ACC.vhd
...........................\................\DDS_ACC_inst.vhd
...........................\................\DDS_ACC_wave0.jpg
...........................\................\DDS_ACC_waveforms.html
...........................\................\DDS_ADD.bsf
...........................\................\DDS_ADD.cmp
...........................\................\DDS_ADD.inc
...........................\................\DDS_ADD.qip
...........................\................\DDS_ADD.vhd
...........................\................\DDS_ADD_inst.vhd
...........................\................\DDS_ADD_wave0.jpg
...........................\................\DDS_ADD_waveforms.html
...........................\................\DDS_Core.bdf
...........................\................\DDS_Core.bsf
...........................\................\DDS_FRE_REG.bsf
...........................\................\DDS_FRE_REG.cmp
...........................\................\DDS_FRE_REG.inc
...........................\................\DDS_FRE_REG.qip
...........................\................\DDS_FRE_REG.vhd
...........................\................\DDS_FRE_REGISTER.bsf
...........................\................\DDS_FRE_REGISTER.cmp
...........................\................\DDS_FRE_REGISTER.inc
...........................\................\DDS_FRE_REGISTER.qip
...........................\................\DDS_FRE_REGISTER.vhd
...........................\................\DDS_FRE_REGISTER_inst.vhd
...........................\................\DDS_FRE_REG_inst.vhd
...........................\................\DDS_PHASE_REGISTER.bsf
...........................\................\DDS_PHASE_REGISTER.cmp
...........................\................\DDS_PHASE_REGIS