Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: chap11 Download
 Description: This program is about learning the language of the case VERILOG to allow readers to quickly master the basic syntax of the language VERILOG, operation, etc.
 To Search:
File list (Check if you may need any files):
chap11
......\account.v
......\clock.v
......\count10.v
......\fre_ctrl.v
......\latch_16.v
......\paobiao.v
......\sell.v
......\song.v
......\traffic.v
    

CodeBus www.codebus.net