Description: Verilog code of UART, tx, rx Jieke
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File list (Check if you may need any files):
uart_top
........\db
........\..\altsyncram_h6e1.tdf
........\..\uart_top.asm.qmsg
........\..\uart_top.asm_labs.ddb
........\..\uart_top.cbx.xml
........\..\uart_top.cmp.bpm
........\..\uart_top.cmp.cdb
........\..\uart_top.cmp.ecobp
........\..\uart_top.cmp.hdb
........\..\uart_top.cmp.kpt
........\..\uart_top.cmp.logdb
........\..\uart_top.cmp.rdb
........\..\uart_top.cmp.tdb
........\..\uart_top.cmp0.ddb
........\..\uart_top.cmp_merge.kpt
........\..\uart_top.db_info
........\..\uart_top.eco.cdb
........\..\uart_top.eda.qmsg
........\..\uart_top.fit.qmsg
........\..\uart_top.hier_info
........\..\uart_top.hif
........\..\uart_top.lpc.html
........\..\uart_top.lpc.rdb
........\..\uart_top.lpc.txt
........\..\uart_top.map.bpm
........\..\uart_top.map.cdb
........\..\uart_top.map.ecobp
........\..\uart_top.map.hdb
........\..\uart_top.map.kpt
........\..\uart_top.map.logdb
........\..\uart_top.map.qmsg
........\..\uart_top.map_bb.cdb
........\..\uart_top.map_bb.hdb
........\..\uart_top.map_bb.logdb
........\..\uart_top.pre_map.cdb
........\..\uart_top.pre_map.hdb
........\..\uart_top.rtlv.hdb
........\..\uart_top.rtlv_sg.cdb
........\..\uart_top.rtlv_sg_swap.cdb
........\..\uart_top.sgdiff.cdb
........\..\uart_top.sgdiff.hdb
........\..\uart_top.sld_design_entry.sci
........\..\uart_top.sld_design_entry_dsc.sci
........\..\uart_top.smp_dump.txt
........\..\uart_top.syn_hier_info
........\..\uart_top.tan.qmsg
........\..\uart_top.tis_db_list.ddb
........\..\uart_top.tmw_info
........\..\uart_top_global_asgn_op.abo
........\incremental_db
........\..............\compiled_partitions
........\..............\...................\uart_top.root_partition.cmp.atm
........\..............\...................\uart_top.root_partition.cmp.dfp
........\..............\...................\uart_top.root_partition.cmp.hdbx
........\..............\...................\uart_top.root_partition.cmp.kpt
........\..............\...................\uart_top.root_partition.cmp.logdb
........\..............\...................\uart_top.root_partition.cmp.rcf
........\..............\...................\uart_top.root_partition.map.atm
........\..............\...................\uart_top.root_partition.map.dpi
........\..............\...................\uart_top.root_partition.map.hdbx
........\..............\...................\uart_top.root_partition.map.kpt
........\..............\README
........\raminfr.v
........\simulation
........\..........\modelsim
........\..........\........\uart_top.sft
........\..........\........\uart_top.vo
........\..........\........\uart_top_modelsim.xrf
........\..........\........\uart_top_v.sdo
........\timescale.v
........\uart_debug_if.v
........\uart_defines.v
........\uart_receiver.v
........\uart_regs.v
........\uart_rfifo.v
........\uart_tfifo.v
........\uart_top.asm.rpt
........\uart_top.done
........\uart_top.eda.rpt
........\uart_top.fit.rpt
........\uart_top.fit.smsg
........\uart_top.fit.summary
........\uart_top.flow.rpt
........\uart_top.map.rpt
........\uart_top.map.summary
........\uart_top.pin
........\uart_top.pof
........\uart_top.qpf
........\uart_top.qsf
........\uart_top.qws
........\uart_top.sof
........\uart_top.tan.rpt
........\uart_top.tan.summary
........\uart_top.v
........\uart_transmitter.v
........\uart_wb.v