Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: Experiment01 Download
 Description: Test a low-level FPGA design flow modeling light, through the board-level debugging
 Downloaders recently: [More information of uploader liulp4972308]
 To Search:
File list (Check if you may need any files):
Experiment01\db\led0_module.db_info
............\..\led0_module.eco.cdb
............\..\led0_module.sld_design_entry.sci
............\..\top_module.db_info
............\..\top_module.eco.cdb
............\led0_module.asm.rpt
............\led0_module.cdf
............\led0_module.done
............\led0_module.dpf
............\led0_module.eda.rpt
............\led0_module.fit.rpt
............\led0_module.fit.summary
............\led0_module.flow.rpt
............\led0_module.map.rpt
............\led0_module.map.summary
............\led0_module.pin
............\led0_module.pof
............\led0_module.qpf
............\led0_module.qsf
............\led0_module.qws
............\led0_module.sof
............\led0_module.tan.rpt
............\led0_module.tan.summary
............\led0_module.v
............\led0_module.v.bak
............\led0_module_assignment_defaults.qdf
............\led1_module.v
............\led1_module.v.bak
............\led2_module.v
............\led2_module.v.bak
............\led3_module.v
............\simulation\modelsim\led0_module.sft
............\..........\........\led0_module.vo
............\..........\........\led0_module_modelsim.xrf
............\..........\........\led0_module_v.sdo
............\top_module.asm.rpt
............\top_module.done
............\top_module.dpf
............\top_module.fit.rpt
............\top_module.fit.summary
............\top_module.flow.rpt
............\top_module.jdi
............\top_module.map.rpt
............\top_module.map.summary
............\top_module.pin
............\top_module.pof
............\top_module.qpf
............\top_module.qsf
............\top_module.qws
............\top_module.sof
............\top_module.tan.rpt
............\top_module.tan.summary
............\top_module.v
............\top_module.v.bak
............\top_module_assignment_defaults.qdf
............\transcript
............\undo_redo.txt
............\simulation\modelsim
............\db
............\incremental_db
............\simulation
Experiment01
    

CodeBus www.codebus.net