进阶实验_06_VGA          ：通过VGA显示一个汉字，800X600@72Hz
............................................................\modelsim
............................................................\........\transcript
............................................................\........\VGA.cr.mti
............................................................\........\vga.do
............................................................\........\VGA.mpf
............................................................\........\vsim.wlf
............................................................\........\work
............................................................\........\....\@a@l@t@e@r@a_@d@e@v@i@c@e_@f@a@m@i@l@i@e@s
............................................................\........\....\..........................................\verilog.asm
............................................................\........\....\..........................................\_primary.dat
............................................................\........\....\..........................................\_primary.vhd
............................................................\........\....\@a@l@t@e@r@a_@m@f_@h@i@n@t_@e@v@a@l@u@a@t@i@o@n
............................................................\........\....\...............................................\_primary.dat
............................................................\........\....\...............................................\_primary.vhd
............................................................\........\....\@a@l@t@e@r@a_@m@f_@m@e@m@o@r@y_@i@n@i@t@i@a@l@i@z@a@t@i@o@n
............................................................\........\....\...........................................................\verilog.asm
............................................................\........\....\...........................................................\_primary.dat
............................................................\........\....\...........................................................\_primary.vhd
............................................................\........\....\@m@f_cycloneiii_pll
............................................................\........\....\...................\_primary.dat
............................................................\........\....\...................\_primary.vhd
............................................................\........\....\@m@f_pll_reg
............................................................\........\....\............\_primary.dat
............................................................\........\....\............\_primary.vhd
............................................................\........\....\@m@f_stratixiii_pll
............................................................\........\....\...................\_primary.dat
............................................................\........\....\...................\_primary.vhd
............................................................\........\....\@m@f_stratixii_pll
............................................................\........\....\..................\_primary.dat
............................................................\........\....\..................\_primary.vhd
............................................................\........\....\@m@f_stratix_pll
............................................................\........\....\................\_primary.dat
............................................................\........\....\................\_primary.vhd
............................................................\........\....\@r@o@m
............................................................\........\....\......\verilog.asm
............................................................\........\....\......\_primary.dat
............................................................\........\....\......\_primary.vhd
............................................................\........\....\@v@g@a_@c@t@l
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