设计与验证VerilogHDL光盘文件\Example-2-1\HelloVlog.v
............................\...........\HelloVlog.vPreview
............................\........3-1\FullAdd.v
............................\...........\transcript
............................\..........2\FullAdd.v
............................\..........3\CRC10.v
............................\........4-1\cnt.prd
............................\...........\cnt.prj
............................\...........\rev_1\cnt1.edf
............................\...........\.....\cnt1.fse
............................\...........\.....\cnt1.srm
............................\...........\.....\cnt1.srr
............................\...........\.....\cnt1.srs
............................\...........\.....\cnt1.tlg
............................\...........\.....\cnt2.edf
............................\...........\.....\cnt2.fse
............................\...........\.....\cnt2.srm
............................\...........\.....\cnt2.srr
............................\...........\.....\cnt2.srs
............................\...........\.....\cnt2.tlg
............................\...........\.....\cnt3.edf
............................\...........\.....\cnt3.fse
............................\...........\.....\cnt3.srm
............................\...........\.....\cnt3.srr
............................\...........\.....\cnt3.srs
............................\...........\.....\cnt3.tlg
............................\...........\.....\syntmp\cnt1.plg
............................\...........\.....\......\cnt2.msg
............................\...........\.....\......\cnt2.plg
............................\...........\.....\......\cnt3.msg
............................\...........\.....\......\cnt3.plg
............................\...........\source\cnt1.v
............................\...........\......\cnt2.v
............................\...........\......\cnt3.v
............................\...........\......\syntmp.msg
............................\...........\示例说明.doc
............................\...........0\bibus\bibus.prd
............................\............\.....\bibus.prj
............................\............\.....\bibus.v
............................\............\.....\decode.v
............................\............\.....\rev_1\bibus.fse
............................\............\.....\.....\bibus.srd
............................\............\.....\.....\bibus.srm
............................\............\.....\.....\bibus.srr
............................\............\.....\.....\bibus.srs
............................\............\.....\.....\bibus.sxr
............................\............\.....\.....\bibus.tcl
............................\............\.....\.....\bibus.tlg
............................\............\.....\.....\bibus.vqm
............................\............\.....\.....\bibus.xrf
............................\............\.....\.....\bibus_cons.tcl
............................\............\.....\.....\bibus_rm.tcl
............................\............\.....\.....\rpt_bibus.areasrr
............................\............\.....\.....\rpt_bibus_areasrr.htm
............................\............\.....\.....\syntmp\bibus.msg
............................\............\.....\.....\......\bibus.plg
............................\............\.....\.....\......\bibus_cons_ui.tcl
............................\............\.....\.....\verif\bibus.vif
............................\............\.....\syntmp.msg
............................\............\complex_bibus\complex_bibus.prd
............................\............\.............\complex_bibus.prj
............................\............\.............\complex_bibus.v
............................\............\.............\complex_bibus2.v
............................\............\.............\counter.v
............................\............\.............\decode.v
............................\............\.............\rev_1\AutoConstraint_complex_bibus.sdc
............................\............\.............\...