Description: _1164.all
entity dec3_8 is
port(a,b,c,s1,s2,s3: in std_logic
y: out std_logic_vector(0 to 7))
end
architecture b of dec3_8 is
signal abc: std_logic_vector(0 to 2)
begin
abc<=a&b&c
process(abc,s1,s2,s3)
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