Description: Two way selector having two input ports of INT1 and INT2, an output port and control port pout, cnt1.
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File list (Check if you may need any files):
exp5
....\db
....\..\prev_cmp_Reg.asm.qmsg
....\..\prev_cmp_Reg.fit.qmsg
....\..\prev_cmp_Reg.map.qmsg
....\..\prev_cmp_Reg.qmsg
....\..\prev_cmp_Reg.tan.qmsg
....\..\Reg.asm.qmsg
....\..\Reg.cbx.xml
....\..\Reg.cmp.cdb
....\..\Reg.cmp.hdb
....\..\Reg.cmp.logdb
....\..\Reg.cmp.rdb
....\..\Reg.cmp.tdb
....\..\Reg.cmp0.ddb
....\..\Reg.db_info
....\..\Reg.eco.cdb
....\..\Reg.fit.qmsg
....\..\Reg.hier_info
....\..\Reg.hif
....\..\Reg.lpc.html
....\..\Reg.lpc.rdb
....\..\Reg.lpc.txt
....\..\Reg.map.cdb
....\..\Reg.map.hdb
....\..\Reg.map.logdb
....\..\Reg.map.qmsg
....\..\Reg.pre_map.cdb
....\..\Reg.pre_map.hdb
....\..\Reg.rtlv.hdb
....\..\Reg.rtlv_sg.cdb
....\..\Reg.rtlv_sg_swap.cdb
....\..\Reg.sgdiff.cdb
....\..\Reg.sgdiff.hdb
....\..\Reg.sld_design_entry.sci
....\..\Reg.sld_design_entry_dsc.sci
....\..\Reg.syn_hier_info
....\..\Reg.tan.qmsg
....\..\Reg.tis_db_list.ddb
....\..\Reg.tmw_info
....\incremental_db
....\..............\compiled_partitions
....\..............\...................\Reg.root_partition.map.kpt
....\..............\README
....\myREG.vhd
....\Reg.asm.rpt
....\Reg.bdf
....\Reg.done
....\Reg.fit.rpt
....\Reg.fit.summary
....\Reg.flow.rpt
....\Reg.map.rpt
....\Reg.map.summary
....\Reg.pin
....\Reg.pof
....\Reg.qpf
....\Reg.qsf
....\Reg.qws
....\Reg.tan.rpt
....\reg.vhd.bak
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