Welcome![Sign In][Sign Up]
Location:
Downloads SourceCode Embeded-SCM Develop VHDL-FPGA-Verilog
Title: s22_DCT Download
 Description: This a code of DCT transformation in verilog ,welcome to download!
 Downloaders recently: [More information of uploader sihaiguoxin]
 To Search:
File list (Check if you may need any files):
s22_DCT\dct\1ddct\.untf
.......\...\.....\1ddct.dhp
.......\...\.....\1ddct.ise
.......\...\.....\1ddct.ise_ISE_Backup
.......\...\.....\automake.log
.......\...\.....\d1_dct.v
.......\...\.....\dct.bld
.......\...\.....\dct.cmd_log
.......\...\.....\dct.lso
.......\...\.....\dct.mrp
.......\...\.....\dct.nc1
.......\...\.....\dct.ncd
.......\...\.....\dct.ngc
.......\...\.....\dct.ngd
.......\...\.....\dct.ngm
.......\...\.....\dct.ngr
.......\...\.....\dct.pad
.......\...\.....\dct.pad_txt
.......\...\.....\dct.par
.......\...\.....\dct.par_nlf
.......\...\.....\dct.pcf
.......\...\.....\dct.placed_ncd_tracker
.......\...\.....\dct.prj
.......\...\.....\dct.routed_ncd_tracker
.......\...\.....\dct.stx
.......\...\.....\dct.syr
.......\...\.....\dct.twr
.......\...\.....\dct.twx
.......\...\.....\dct.versim_par
.......\...\.....\dct.xpi
.......\...\.....\dct_map.ncd
.......\...\.....\dct_map.ngm
.......\...\.....\dct_pad.csv
.......\...\.....\dct_pad.txt
.......\...\.....\dct_summary.html
.......\...\.....\dct_test.cmd_log
.......\...\.....\dct_test.lso
.......\...\.....\dct_test.prj
.......\...\.....\dct_test.syr
.......\...\.....\dct_test_summary.html
.......\...\.....\dct_test_vhdl.prj
.......\...\.....\dct_timesim.nlf
.......\...\.....\dct_timesim.sdf
.......\...\.....\dct_timesim.v
.......\...\.....\dct_vhdl.prj
.......\...\.....\idtest.ant
.......\...\.....\idtest.fdo
.......\...\.....\idtest.jhd
.......\...\.....\idtest.tbw
.......\...\.....\idtest.tdo
.......\...\.....\idtest.tfw
.......\...\.....\idtest.timesim_tfw
.......\...\.....\idtest.udo
.......\...\.....\idtest.xwv
.......\...\.....\idtest.xwv_bak
.......\...\.....\idtest_bencher.prj
.......\...\.....\Project.dhp
.......\...\.....\results.txt
.......\...\.....\transcript
.......\...\.....\vsim.wlf
.......\...\.....\work\dct\verilog.asm
.......\...\.....\....\...\_primary.dat
.......\...\.....\....\...\_primary.vhd
.......\...\.....\....\glbl\verilog.asm
.......\...\.....\....\....\_primary.dat
.......\...\.....\....\....\_primary.vhd
.......\...\.....\....\idtest\verilog.asm
.......\...\.....\....\......\_primary.dat
.......\...\.....\....\......\_primary.vhd
.......\...\.....\....\_info
.......\...\.....\xst\work\hdllib.ref
.......\...\.....\...\....\vlg27\dct.bin
.......\...\.....\...\....\...36\dct__test.bin
.......\...\.....\_ngo\netlist.lst
.......\...\.....\._projnav\1ddct.gfl
.......\...\.....\.........\1ddct_flowplus.gfl
.......\...\.....\.........\dct.xst
.......\...\.....\.........\dct_test.xst
.......\...\.....\.........\ednTOngd_tcl.rsp
.......\...\.....\.........\nc1TOncd_tcl.rsp
.......\...\.....\.........\netgen_par_tcl.rsp
.......\...\.....\.........\runXst_tcl.rsp
.......\...\.....\.........\sumrpt_tcl.rsp
.......\...\.....\__projnav.log
.......\...\introduce.txt
.......\...\rtl\d1_dct.v
.......\...\...\d2_dct.v
.......\...\1ddct\xst\dump.xst\dct.prj\ngx\notopt
.......\...\.....\...\........\.......\...\opt
.......\...\.....\...\........\..._test.prj\ngx\notopt
.......\...\.....\...\........\............\...\opt
.......\...\.....\...\........\....prj\ngx
.......\...\.....\...\........\..._test.prj\ngx
.......\...\.....\...\........\dct.prj
.......\...\.....\...\........\dct_test.prj
.......\...\.....\...\work\vlg27
.......\...\.....\...\....\vlg36
.......\...\.....\work\dct
.......\...\.....\....\glbl
.......\...\.....\....\idtest
    

CodeBus www.codebus.net