Description: VERILOG a serial port to receive example, can receive a single byte, appropriate to add a small amount of code can be any byte receive.
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File list (Check if you may need any files):
uart_verilog\74segled.v.bak
............\db\uart_v.db_info
............\..\uart_v.eco.cdb
............\..\uart_v.sld_design_entry.sci
............\rcvr.bsf
............\rcvr.v
............\rcvr.v.bak
............\segmain.bsf
............\segmain.v
............\setup.tcl
............\setup.tcl.bak
............\txmit.bsf
............\txmit.v
............\txmit.v.bak
............\uart.bsf
............\uart.v
............\uart.v.bak
............\uart_send.bsf
............\uart_send.v
............\uart_send.v.bak
............\uart_v.asm.rpt
............\uart_v.bdf
............\uart_v.done
............\uart_v.fit.rpt
............\uart_v.fit.smsg
............\uart_v.fit.summary
............\uart_v.flow.rpt
............\uart_v.map.rpt
............\uart_v.map.smsg
............\uart_v.map.summary
............\uart_v.pin
............\uart_v.pof
............\uart_v.qpf
............\uart_v.qsf
............\uart_v.qws
............\uart_v.sof
............\uart_v.sta.rpt
............\uart_v.sta.summary
............\uart_v.tan.rpt
............\uart_v.tan.summary
............\db
uart_verilog
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